代码搜索：FSM
找到约 3,748 项符合「FSM」的源代码
代码结果 3,748
www.eeworm.com/read/453468/7419137
h fsm.h
#ifndef _FSM_H_
#define _FSM_H_
#include
#include
using namespace std;
enum ENUM_FSM_CONDITION_ID
{
FCID_MOVE_COMPLETE,
FCID_ENOUGH_REST,
FCID_TARGET_FOUND,
FCID_
www.eeworm.com/read/449305/7509013
set fsm.set
FSMSET_CUTHEADER=0
FSMSET_GENCOMMENTS=1
FSMSET_USEDEFINE=1
FSMSET_OMITGENNULL=0
FSMSET_ENABLEPARSING=1
FSMSET_TB1=1
FSMSET_TB2=1
FSMSET_TB3=1
FSMSET_HDLSTYLE=0
FSMSET_PROCNUM=1
FSMSET_ASSIGN
www.eeworm.com/read/398898/7912202
vhd fsm.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Constants.all;
entity FSM is
port (reset, clk : in std_logic;
strobe : out std_logic;
sample : out std_logic;
www.eeworm.com/read/198751/7912565
fsm fsmviewer.fsm
fsm_options -device {state[3:0]}
define_state STATE_STOP 00 {f:\lizheng\fiberoptical\fpga\pci_bridge_guest_uart\wb_master.v} 106 3 106 12
state_output STATE_STOP {state[0]} 1
define_state STATE
www.eeworm.com/read/433434/7930388
txt fsm.txt
module fsm(Clock,Reset,A,K2,K1);
input Clock,Reset,A;
output K2,K1;
reg K2,K1;
reg [1:0] state;
parameter Idle =2'b00,Start =2'b01;
Stop=2'b10,Clear=2'b11;
always @(posedge Clock)
if(
www.eeworm.com/read/297875/7990999
v fsm.v
module FSM(clk,clr,out,start,step2,step3);
input clk,clr,start,step2,step3;
output[2:0] out;
reg[2:0] out;
reg[1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,
state2=2'b11,sta
www.eeworm.com/read/297200/8045416
v fsm.v
module pg20_3 ( a, b, p, g );
input [19:0] a;
input [19:0] b;
output [19:0] p;
output [19:0] g;
XOR2X1 U1 ( .A(b[6]), .B(a[6]), .Y(p[6]) );
XOR2X1 U2 ( .A(b[11]), .B(a[11]), .Y(p[11]) )
www.eeworm.com/read/296104/8121904
v fsm.v
module FSM(clk,clr,out,start,step2,step3);
input clk,clr,start,step2,step3;
output[2:0] out;
reg[2:0] out;
reg[1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,
state2=2'b11,sta
www.eeworm.com/read/296097/8122464
v fsm.v
module FSM(clk,clr,out,start,step2,step3);
input clk,clr,start,step2,step3;
output[2:0] out;
reg[2:0] out;
reg[1:0] state,next_state;
parameter state0=2'b00,state1=2'b01,
state2=2'b11,sta
www.eeworm.com/read/144319/12802691
c fsm.c
/* fsm.c - {Link, IP} Control Protocol Finite State Machine */
/* Copyright 1995 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
* Copyright (c) 1989 Carnegie Mellon University.
* All ri