fsm.txt

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module fsm(Clock,Reset,A,K2,K1);

input Clock,Reset,A;
output K2,K1;
reg K2,K1;
reg [1:0] state;

parameter Idle =2'b00,Start =2'b01;
Stop=2'b10,Clear=2'b11;

always @(posedge Clock)
   if(!Reset)
         begin
           state<=Idle;
           K2<=0;
           K1<=0;
         end
   else
     case(state)
       Idle: begin
             if(A) begin
                   state<=Start;
                   K1<=0;
                   end
             else state<=Idle;
             end
       
        Start:begin
              if(A) begin
                      state<=Clear;
                      K2<=1;
                    end
               else  state<=Stop;
               end
        Clear:begin
              if(!A) begin
                     state<=Idle;
                     K2<=0;
                     K1<=1;
                     end
              else   state<=Clear;
              end
endcase
endmodule