fsm.set

This is a simple pulse generator. It generates a pulse

FSMSET_CUTHEADER=0
FSMSET_GENCOMMENTS=1
FSMSET_USEDEFINE=1
FSMSET_OMITGENNULL=0
FSMSET_ENABLEPARSING=1
FSMSET_TB1=1
FSMSET_TB2=1
FSMSET_TB3=1
FSMSET_HDLSTYLE=0
FSMSET_PROCNUM=1
FSMSET_ASSIGNTYPE=0
FSMSET_GENHANDCPP=0
FSMSET_GENSCMAIN=0
FSMSET_VHDLSHARED=0
FSMSET_IEEE93=0
FSMSET_RFEDGE=0
FSMSET_SCENABLE=0
FSMSET_USEVERILOGPARSER=0
FSMSET_SYNTHESIS_TOOL=SynopsysFPGAExpress
FSMSET_SYNTHESIS_ATTRIBUTES=1
FSMSET_SYNTHESIS_ENUM_ENCODING_STYLE=0
FSMSET_USESPACES=0
FSMSET_DESIGNNAME=generator
FSMSET_PROCNUM_VERILOG=2