代码搜索:FPGA EDK
找到约 10,000 项符合「FPGA EDK」的源代码
代码结果 10,000
www.eeworm.com/read/490831/1195816
lst netlist.lst
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\iic\ise\iic\i2c.ngc 1140949829
OK
www.eeworm.com/read/219809/4845973
help tech.in.help
Prompt for target technology
CONFIG_SYN_INFERRED
Selects the target technology for memory and pads.
The following are available:
- Inferred: Generic FPGA or ASIC targets if your synthesis to
www.eeworm.com/read/325655/3481331
lst netlist.lst
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\iic\ise\iic\i2c.ngc 1140949829
OK
www.eeworm.com/read/318858/3561870
lst netlist.lst
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\iic\ise\iic\i2c.ngc 1140949829
OK
www.eeworm.com/read/315673/3616879
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_core is
generic(
idle : integer := 1;
start : integer := 17;
write : integer := 2;
www.eeworm.com/read/436752/1845007
rsp runxst_tcl.rsp
set allSynthModules {pwron.MOD reset.MOD clkgen.MOD ps2dec.MOD fpga_40Aps2.MOD}
www.eeworm.com/read/436752/1845030
lst netlist.lst
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\iic\ise\iic\i2c.ngc 1140949829
OK
www.eeworm.com/read/436462/1848663
lst netlist.lst
f:\trainsilicon\fpgaschool\testcade\fpga40xc200\basic2\iic\ise\iic\i2c.ngc 1140949829
OK
www.eeworm.com/read/334090/12640211
gel gsample_arm9_emif.gel
/* EMIF Configuration GEL file
This GEL file collects every EMIFF & EMIFS possible configurations
according to the Memory Module available on Thalassa & the FPGA EMIFS mode
*/
menuitem "EMIF
www.eeworm.com/read/315669/13538554
srd cmos_fifo_usb.srd
f "noname"; #file 0
f "c:\libero\synplify\synplify_88a1\lib\proasic\proasic3.v"; #file 1
f "h:\fpga_test\cmos_fifo_usb\smartgen\two_port1280x8\two_port1280x8.v"; #file 2
f "h:\fpga_test\cmos_fifo_u