gsample_arm9_emif.gel

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/* EMIF Configuration GEL file

This GEL file collects every EMIFF & EMIFS possible configurations
according to the Memory Module available on Thalassa & the FPGA EMIFS mode

*/

menuitem "EMIFF"

/* 
   EMIF Fast Registers configuration
   For Elpida 256M bits DDR mobile RAM 
   16M words, 16 bits data bus, 4 banks, 9 columns, 13 row
*/
hotmenu EMIFF_Setup_DDRAM()
{

  int i, SDRAM_Op_Reg, SDRAM_Config_Reg;

  SDRAM_Op_Reg = (*(int*)0xFFFECC80);
  SDRAM_Config_Reg = (*(int*)0xFFFECC20);
  
  
  // SPARE Register setting at NEPTUNE Configuration level
  (*(int*)0xFFFE102C) = 1;

  // DDR Set Up if not yet done
  if ( ((SDRAM_Op_Reg & 0x7) != 0x7) && ((SDRAM_Config_Reg & 0x000081F6) != 0x000081F6) ){

    (*(int*)0xFFFECC80) = 0x07; 		/* DDR Operation addr Mobile DDR, HPHB mode */
    (*(int*)0xFFFECC20) = 0x0003F7F6;   /* SDRAM Config */    
    (*(int*)0xFFFECC84) = 0x07;  		/* Manual CMD Addr, CKE high */
    (*(int*)0xFFFECC84) = 0x00; 		/* Manual CMD Addr NOP command */
    for (i = 0; i< 5; i++)   		    /* Delay Loop */
    (*(int*)0xFFFECC84) = 0x01; 		/* Precharge Command */
    (*(int*)0xFFFECC84) = 0x02; 		/* Auto-refresh command */
    (*(int*)0xFFFECC84) = 0x02; 		/* Auto-refresh command */
    (*(int*)0xFFFECC70) = 0x33;         /* Sdram MRS Register (new)  */
    (*(int*)0xFFFECC78) = 0x00; 		/* EMRS1 self refresh all banks */
    (*(int*)0xFFFECCC0) = 0x06;         /* DLL URD Control Register */
    (*(int*)0xFFFECCCC) = 0x06;         /* DLL LRD Control Register */
    (*(int*)0xFFFECC64) = 0x06;         /* DLL WRT Control Register */


    GEL_TextOut("DDR interface configured\n","result");

  } else GEL_TextOut("DDR interface already configured\n","result");
  
  return;
}

/************ ADDED BY YUBO TO USE SDR SDRAM AS OUR PLATFORM 2005-09-16 ********************/

hotmenu EMIFF_Setup_SDRRAM()
   {
     int i;
     (*(int*)0xFFFECC80) = 0x06;			/*Mobile SDRAM */
     (*(int*)0xFFFECC20) = 0x000032B4;		        /* EMIFF (nCS4) configuration,tc_clk=13M */
     (*(int*)0xFFFECC84) = 0x07;                        /* Manual CMD Addr, CKE high */
     (*(int*)0xFFFECC84) = 0x00;                        /* Manual CMD Addr NOP command */
     
     for (i = 0; i< 5; i++);                            /* Delay Loop */
     
     (*(int*)0xFFFECC84) = 0x01;                        /* Precharge Command */
     (*(int*)0xFFFECC84) = 0x02;                        /* Auto-refresh command */
     (*(int*)0xFFFECC84) = 0x02;                        /* Auto-refresh command */
     (*(int*)0xFFFECC70) = 0x00000037;		        /* MRS (nCS4) initialization  */
     
     GEL_TextOut("SDR interface enable\n","result");
   
    }


hotmenu EMIFF_Setup_SDRAM()
{

  (*(int*)0xFFFECC20) = 0x0003F7F6; // Auto Refresh, SDRAM, 4bank * 16bits * 4MG, Power Management disabled
  //(*(int*)0xFFFECC24) = 0x00000027; // CAS Latency = 2
  (*(int*)0xFFFECC24) = 0x00000037; // CAS Latency = 3


  GEL_TextOut("SDRAM interface configured\n","result");

  return;
}


/* Memory Module #2, Option #2 & EMIFS CPLD mode = 0  
   CS0 = Internal Boot ROM
   CS1 = NAND Flash 64Mb x 8bits (BGA)	K9K1208Q0C-DIB0
   CS2 = Ethernet + FPGA
   CS3 = SRAM Micron 4M x 16bits MT45W4MW16BFB 70ns */
EMIFS_Setup_Memory2_Opt2_CPLD0()
{

  // SRAM I/F configuration on CS3
  (*(int*)0xFFFECC1C) = 0x00404088;		/* EMIFS CS3 Configuration Register : A/D Multiplexed, 8 RWS, 0 WWS, WELEN = 4, 1 BT WST, Asynchronous Read mode & Ref_Clk = TC_Clock */
  (*(int*)0xFFFECC5C) = 0x00000103;		/* EMIFS CS3 Advanced Configuration Register : ADV hold = 2 Ref_Clk cycles, OE SETUP = 3 */

  GEL_TextOut("SRAM interface configured on CS3\n","result");

  return;
}