tech.in.help

free hardware ip core about sparcv8,a soc cpu in vhdl

Prompt for target technology
CONFIG_SYN_INFERRED
  Selects the target technology for memory and pads. 
  The following are available:

  - Inferred: Generic FPGA or ASIC targets if your synthesis tool
    is capable of inferring RAMs and pads automatically.

  - Actel ProAsic/P/3 and Axellerator FPGAs
  - Altera: Any Altera FPGA family           
  - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS
  - IHP25: IHP 0.25 um CMOS
  - Lattice : EC/ECP/XP FPGAs
  - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries
  - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries
  - Xilinx-Spartan3E: Xilinx Spartan3E libraries
  - Xilinx-Virtex/E: Xilinx Virtex/E libraries
  - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries


Ram library
CONFIG_MEM_VIRAGE
  Select RAM generators for ASIC targets. 

Infer ram
CONFIG_SYN_INFER_RAM
  Say Y here if you want the synthesis tool to infer your
  RAM automatically. Say N to directly instantiate technology-
  specific RAM cells for the selected target technology package.

Infer pads
CONFIG_SYN_INFER_PADS
  Say Y here if you want the synthesis tool to infer pads.
  Say N to directly instantiate technology-specific pads from
  the selected target technology package.

No async reset
CONFIG_SYN_NO_ASYNC
  Say Y here if you disable asynchronous reset in some of the IP cores.
  Might be necessary if the target library does not have cells with
  asynchronous set/reset.