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FPGA 的代码
input.c
/*
* \brief DOpE input driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
input.c
/*
* \brief DOpE input driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
input.c
/*
* \brief DOpE input driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
input.c
/*
* \brief DOpE input driver module for Charon's FPGA board
* \date 2005-02-04
* \author Norman Feske
*/
/*
* Copyright (C) 2005-2008 Norman Feske
microblaze_logo.h
/* GIMP header image file format (RGB): C:\FPGA\testing\microblaze_external_prog\mb-dope\test\microblaze_logo.h */
/*static unsigned int width = 269;
static unsigned int height = 51;
*/
static ch
irq-mb93091.c
/* irq-mb93091.c: MB93091 FPGA interrupt handling
*
* Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you
irq-mb93093.c
/* irq-mb93093.c: MB93093 FPGA interrupt handling
*
* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you
program.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\verilo
program.xco
# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\verilo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_a_top is
port(
DSP_ACK : out vl_logic;
DSP_ADDR : in vl_logic_vector(31 downto 0);
DSP_A_RESET