program.xco

Xilinx的培训教程的源码 virtex

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\xupv2pro\labsolutions\verilog\lab6
SET speedgrade = -7
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc2vp30
SET implementationfiletype = ngc
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff896
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 2.1
# END Select
# BEGIN Parameters
CSET write_depth_a=1024
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET write_width_a=18
CSET write_width_b=18
CSET use_regcea_pin=false
CSET primitive=8kx2
CSET memory_type=Dual_Port_ROM
CSET byte_size=9
CSET disable_out_of_range_warnings=false
CSET use_regceb_pin=false
CSET remaining_memory_locations=0
CSET use_byte_write_enable=false
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET component_name=program
CSET assume_synchronous_clk=false
CSET disable_collision_warnings=false
CSET algorithm=Minimum_Area
CSET fill_remaining_memory_locations=false
CSET register_output_of_memory_primitives=false
CSET use_ssra_pin=false
CSET read_width_a=18
CSET read_width_b=18
CSET register_output_of_memory_core=false
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET load_init_file=true
CSET coe_file=C:/XUP/Markets/PLDs/Workshops/courses/v82_fpga_flow/xupv2pro/labsolutions/verilog/lab6/Assembler/PROGRAM.COE
CSET use_ssrb_pin=false
CSET collision_warnings=ALL
# END Parameters
GENERATE