_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity fpga_a_top is
    port(
        DSP_ACK         : out    vl_logic;
        DSP_ADDR        : in     vl_logic_vector(31 downto 0);
        DSP_A_RESET     : out    vl_logic;
        DSP_BACKOFF     : out    vl_logic;
        DSP_BMS_A       : in     vl_logic;
        DSP_BMS_B       : in     vl_logic;
        DSP_BRST        : inout  vl_logic;
        DSP_BUS_REQ     : out    vl_logic_vector(3 downto 0);
        DSP_BUSLOCK     : in     vl_logic;
        DSP_BUSMASTER_A : in     vl_logic;
        DSP_BUSMASTER_B : in     vl_logic;
        DSP_B_RESET     : out    vl_logic;
        DSP_CPA         : inout  vl_logic;
        DSP_DATA        : inout  vl_logic_vector(31 downto 0);
        DSP_DMAR0_A     : out    vl_logic;
        DSP_DMAR0_B     : out    vl_logic;
        DSP_DMAR1_A     : out    vl_logic;
        DSP_DMAR1_B     : out    vl_logic;
        DSP_DMAR2_A     : out    vl_logic;
        DSP_DMAR2_B     : out    vl_logic;
        DSP_DMAR3_A     : out    vl_logic;
        DSP_DMAR3_B     : out    vl_logic;
        DSP_DPA         : inout  vl_logic;
        DSP_FLAG0_A     : inout  vl_logic;
        DSP_FLAG0_B     : inout  vl_logic;
        DSP_FLAG1_A     : inout  vl_logic;
        DSP_FLAG1_B     : inout  vl_logic;
        DSP_HOSTBUSGRA  : inout  vl_logic;
        DSP_HOSTBUSREQ  : out    vl_logic;
        DSP_IOEN_A      : in     vl_logic;
        DSP_IOEN_B      : in     vl_logic;
        DSP_IORD_A      : in     vl_logic;
        DSP_IORD_B      : in     vl_logic;
        DSP_IOWR_A      : in     vl_logic;
        DSP_IOWR_B      : in     vl_logic;
        DSP_IRQ0_A      : out    vl_logic;
        DSP_IRQ1_A      : out    vl_logic;
        DSP_IRQ1_B      : out    vl_logic;
        DSP_MEM_SEL     : in     vl_logic_vector(1 downto 0);
        DSP_MEM_SELH    : in     vl_logic;
        DSP_RD          : in     vl_logic;
        DSP_WRH         : in     vl_logic;
        DSP_WRL         : in     vl_logic;
        E_RXCLK01       : out    vl_logic;
        E_RXDATA        : out    vl_logic_vector(7 downto 0);
        E_RXENB0        : in     vl_logic;
        E_RXEOF0        : out    vl_logic;
        E_RXERR0        : out    vl_logic;
        E_RXFA0         : out    vl_logic;
        E_RXPRTY0       : out    vl_logic;
        E_RXSOF0        : out    vl_logic;
        E_RXVAL0        : out    vl_logic;
        E_TXCLK01       : out    vl_logic;
        E_TXDATA        : in     vl_logic_vector(7 downto 0);
        E_TXENB0        : in     vl_logic;
        E_TXEOF0        : in     vl_logic;
        E_TXERR0        : in     vl_logic;
        E_TXFA0         : out    vl_logic;
        E_TXPRTY0       : in     vl_logic;
        E_TXSOF0        : in     vl_logic;
        FPGA_ADR        : in     vl_logic_vector(23 downto 22);
        FPGA_ADDR       : in     vl_logic_vector(15 downto 0);
        FPGA_A_CHIPCLK  : in     vl_logic;
        FPGA_A_CS       : in     vl_logic_vector(2 downto 1);
        FPGA_A_DSPCLK   : in     vl_logic;
        FPGA_A_EXPCLK   : in     vl_logic;
        FPGA_A_INT      : out    vl_logic_vector(2 downto 1);
        FPGA_A_IOWAIT   : out    vl_logic;
        FPGA_A_LED      : out    vl_logic_vector(15 downto 0);
        FPGA_A_LOCAL_CHIP_IN: in     vl_logic;
        FPGA_A_PP2S_IN  : in     vl_logic;
        FPGA_A_RESET    : in     vl_logic_vector(2 downto 1);
        FPGA_A_RDY      : out    vl_logic;
        FPGA_A_RD       : in     vl_logic;
        FPGA_A_UART_RX  : in     vl_logic;
        FPGA_A_UART_RX2 : in     vl_logic;
        FPGA_A_UART_TX  : out    vl_logic;
        FPGA_A_UART_TX2 : out    vl_logic;
        FPGA_A_WR       : in     vl_logic;
        FPGA_DATA       : inout  vl_logic_vector(15 downto 0);
        L0ACKIN_A       : out    vl_logic;
        L0BCMOUT_A      : in     vl_logic;
        L0CLKOUT_P_A    : in     vl_logic;
        L0DATOUT0_P_A   : in     vl_logic;
        L0DATOUT1_P_A   : in     vl_logic;
        L0DATOUT2_P_A   : in     vl_logic;
        L0DATOUT3_P_A   : in     vl_logic;
        L0CLKIN_P_A     : out    vl_logic;
        L0ACKOUT_A      : in     vl_logic;
        L0BCMPIN_A      : out    vl_logic;
        L0DATIN0_P_A    : out    vl_logic;
        L0DATIN1_P_A    : out    vl_logic;
        L0DATIN2_P_A    : out    vl_logic;
        L0DATIN3_P_A    : out    vl_logic;
        L1ACKIN_A       : out    vl_logic;
        L1BCMOUT_A      : in     vl_logic;
        L1CLKOUT_P_A    : in     vl_logic;
        L1DATOUT0_P_A   : in     vl_logic;
        L1DATOUT1_P_A   : in     vl_logic;
        L1DATOUT2_P_A   : in     vl_logic;
        L1DATOUT3_P_A   : in     vl_logic;
        L0CLKIN_P_B     : out    vl_logic;
        L0ACKOUT_B      : in     vl_logic;
        L0BCMPIN_B      : out    vl_logic;
        L0DATIN0_P_B    : out    vl_logic;
        L0DATIN1_P_B    : out    vl_logic;
        L0DATIN2_P_B    : out    vl_logic;
        L0DATIN3_P_B    : out    vl_logic;
        TST_IO          : out    vl_logic_vector(1 downto 0);
        WP_GPIO         : inout  vl_logic_vector(1 downto 0)
    );
end fpga_a_top;