_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 34 行

library verilog;
use verilog.vl_types.all;
entity ctc_decoder_core is
    port(
        core_gnt        : in     vl_logic;
        wr_over         : in     vl_logic;
        rx2ctrl_length  : in     vl_logic_vector(15 downto 0);
        rx2ctrl_type    : in     vl_logic_vector(2 downto 0);
        rx2ctrl_frame_end_flag: in     vl_logic_vector(2 downto 0);
        rx2ctrl_inst    : in     vl_logic_vector(1 downto 0);
        rx2ctrl_code_rate: in     vl_logic_vector(2 downto 0);
        rx2ctrl_modu_type: in     vl_logic_vector(1 downto 0);
        rx2ctrl_bnum    : in     vl_logic_vector(15 downto 0);
        rx2ctrl_fnum    : in     vl_logic_vector(7 downto 0);
        rx2ctrl_miter   : in     vl_logic_vector(3 downto 0);
        rx2ctrl_segId   : in     vl_logic_vector(3 downto 0);
        dec_finish      : out    vl_logic;
        core_req        : out    vl_logic;
        dpram1_rddat    : in     vl_logic_vector(11 downto 0);
        dpram1_rdadr    : out    vl_logic_vector(11 downto 0);
        dpram1_rd       : out    vl_logic;
        dpram2_rddat    : in     vl_logic_vector(23 downto 0);
        dpram2_rdadr    : out    vl_logic_vector(11 downto 0);
        dpram2_rd       : out    vl_logic;
        ctc_fifo_empty  : in     vl_logic;
        ctc_fifo_full   : in     vl_logic;
        ctc_fifo_usedw  : in     vl_logic_vector(8 downto 0);
        ctc_fifo_wrdat  : out    vl_logic_vector(31 downto 0);
        ctc_fifo_wrreq  : out    vl_logic;
        sys_clk         : in     vl_logic;
        reset_b         : in     vl_logic
    );
end ctc_decoder_core;