_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity mod_max4 is
    generic(
        STATE_MATRIC_WIDTH: integer := 12
    );
    port(
        a               : in     vl_logic_vector;
        b               : in     vl_logic_vector;
        c               : in     vl_logic_vector;
        d               : in     vl_logic_vector;
        e               : out    vl_logic_vector
    );
end mod_max4;