代码搜索结果

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

# User constrains file for the "Virtex-II V2MB1000 Development kit", # the "P160 Communications module" and the "P160 Prototype module". # There are described all of FPGA used pins. Some of nets are

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

// E:\FPGA\CLKGEN // Verilog Test fixture created by // HDL Bencher 6.1i // Thu Apr 05 11:33:31 2007 // // Notes: // 1) This test fixture has been automatically generated from // your Test B

// E:\FPGA\CLKGEN // Verilog Test fixture created by // HDL Bencher 6.1i // Fri May 18 22:21:23 2007 // // Notes: // 1) This test fixture has been automatically generated from // your Test B

-- A First-in First-out Memory -- a first-in first out memory, uses a synchronising clock -- generics allow fifos of different sizes to be instantiated -- download from: www.fpga.com.cn & www.pld.c

Success Decoder E:\Easy FPGA030\Decoder\synthesis\Decoder.edn

[General Information] 书名=基于QUARTUS 2的FPGA/CPLD设计 作者=李洪伟 袁斯华编著 页数=282 SS号=11592888 出版日期=2006年04月

Output: VHDL File Type : VHDL From : Project [FPGA_Project1.PrjFpg] Generated File[CPU.VHD] Files Generated : 1 Documents Printed : 0 Finished Output Generation At 16:07:45 On 2010-