leon3mp.ucf

LEON3 SOC GRlip IP core. Memory controller.

# User constrains file for the "Virtex-II V2MB1000 Development kit",
# the "P160 Communications module" and the "P160 Prototype module".
# There are described all of FPGA used pins. Some of nets are 
# duplicated in many groups with different net names. If you need, 
# you can change name of the nets.
#
# Roman Bartosinski ([e-mail])
# Revision 1.1, 2003-07-29



###################################################
# Main board - Virtex-II V2MB1000 Development kit #
###################################################

# DDR Memory 32MB - Address[12:0],Data[15:0],BS[1:0],LDM,UDM,LDQS,UDQS,CSn,RASn,CASn,WEn,CLKE,CLKn,CLK
NET "ddr_ad(0)"     LOC =  B18 | IOSTANDARD = SSTL2_I; # Address 0
NET "ddr_ad(1)"     LOC =  A18 | IOSTANDARD = SSTL2_I; # Address 1
NET "ddr_ad(2)"     LOC =  B17 | IOSTANDARD = SSTL2_I; # Address 2
NET "ddr_ad(3)"     LOC =  A17 | IOSTANDARD = SSTL2_I; # Address 3
NET "ddr_ad(4)"     LOC =  N17 | IOSTANDARD = SSTL2_I; # Address 4
NET "ddr_ad(5)"     LOC =  P18 | IOSTANDARD = SSTL2_I; # Address 5
NET "ddr_ad(6)"     LOC =  P17 | IOSTANDARD = SSTL2_I; # Address 6
NET "ddr_ad(7)"     LOC =  M18 | IOSTANDARD = SSTL2_I; # Address 7
NET "ddr_ad(8)"     LOC =  M19 | IOSTANDARD = SSTL2_I; # Address 8
NET "ddr_ad(9)"     LOC =  M20 | IOSTANDARD = SSTL2_I; # Address 9
NET "ddr_ad(10)"    LOC =  A19 | IOSTANDARD = SSTL2_I; # Address 10
NET "ddr_ad(11)"    LOC =  N18 | IOSTANDARD = SSTL2_I; # Address 11
NET "ddr_ad(12)"    LOC =  N20 | IOSTANDARD = SSTL2_I; # Address 12
NET "ddr_dq(0)"     LOC =  Y21 | IOSTANDARD = SSTL2_II; # Data 0
NET "ddr_dq(1)"     LOC =  Y22 | IOSTANDARD = SSTL2_II; # Data 1
NET "ddr_dq(2)"     LOC =  W21 | IOSTANDARD = SSTL2_II; # Data 2
NET "ddr_dq(3)"     LOC =  V21 | IOSTANDARD = SSTL2_II; # Data 3
NET "ddr_dq(4)"     LOC =  V22 | IOSTANDARD = SSTL2_II; # Data 4
NET "ddr_dq(5)"     LOC =  U21 | IOSTANDARD = SSTL2_II; # Data 5
NET "ddr_dq(6)"     LOC =  U22 | IOSTANDARD = SSTL2_II; # Data 6
NET "ddr_dq(7)"     LOC =  T21 | IOSTANDARD = SSTL2_II; # Data 7
NET "ddr_dq(8)"     LOC =  R20 | IOSTANDARD = SSTL2_II; # Data 8
NET "ddr_dq(9)"     LOC =  R19 | IOSTANDARD = SSTL2_II; # Data 9
NET "ddr_dq(10)"    LOC =  T20 | IOSTANDARD = SSTL2_II; # Data 10
NET "ddr_dq(11)"    LOC =  T19 | IOSTANDARD = SSTL2_II; # Data 11
NET "ddr_dq(12)"    LOC =  U19 | IOSTANDARD = SSTL2_II; # Data 12
NET "ddr_dq(13)"    LOC =  V20 | IOSTANDARD = SSTL2_II; # Data 13
NET "ddr_dq(14)"    LOC =  V19 | IOSTANDARD = SSTL2_II; # Data 14
NET "ddr_dq(15)"    LOC =  W20 | IOSTANDARD = SSTL2_II; # Data 15
NET "ddr_ba(0)"       LOC =  M21 | IOSTANDARD = SSTL2_I; # Bank Select 0
NET "ddr_ba(1)"       LOC =  B19 | IOSTANDARD = SSTL2_I; # Bank Select 1
NET "ddr_dm(0)"         LOC =  R21 | IOSTANDARD = SSTL2_I; # Low Write Mask
NET "ddr_dm(1)"         LOC =  T22 | IOSTANDARD = SSTL2_I; # High Write Mask
NET "ddr_dqs(0)"        LOC =  P20 | IOSTANDARD = SSTL2_I; # Low Write/ReadData Strobe
NET "ddr_dqs(1)"        LOC =  P19 | IOSTANDARD = SSTL2_I; # High Write/Read Data Strobe
NET "ddr_cs0b"          LOC =  N22 | IOSTANDARD = SSTL2_I; # Chip Select
NET "ddr_rasb"         LOC =  N21 | IOSTANDARD = SSTL2_I; # Row Address Strobe
NET "ddr_casb"         LOC =  P21 | IOSTANDARD = SSTL2_I; # Column Adress Strobe
NET "ddr_web"          LOC =  R22 | IOSTANDARD = SSTL2_I; # Write Enable
NET "ddr_clk0"         LOC =  D12 | IOSTANDARD = SSTL2_I; # Clock
NET "ddr_clk0b"        LOC =  E12 | IOSTANDARD = SSTL2_I; # Clock
NET "ddr_cke0"         LOC =  N19 | IOSTANDARD = SSTL2_I; # Clock Enable
NET "ddr_clk_fb"       LOC =  F13 | IOSTANDARD = SSTL2_I; # Clock feed-back

# Clock generation - on-board oscillators 100Mhz and 24MHz
NET "clk_100mhz"      LOC =  B11; # On-board 100 MHz Oscillator
NET "clk_24"          LOC =  A11; # On-board 24 MHz Oscillator

# Reset circuit - RESETn
NET "resetn"          LOC =  B6 ; # FPGA_RESETn (push-button switch SW3)

# User 7-segment display (common cathode - active high)
#    - A2 -     - A1 - 
#   |      |   |      |
#   F2    B2   F2    B1
#   |      |   |      |
#    - G2 -     - G1 - 
#   |      |   |      |
#   E2    C2   E1    C1
#   |      |   |      |
#    - D2 -     - D1 - 
NET "segm_lo(0)"       LOC =  D9 ; # 7-segment LED display1, Segment A
NET "segm_lo(1)"       LOC =  C9 ; # 7-segment LED display1, Segment B
NET "segm_lo(2)"       LOC =  F11; # 7-segment LED display1, Segment C
NET "segm_lo(3)"       LOC =  F9 ; # 7-segment LED display1, Segment D
NET "segm_lo(4)"       LOC =  F10; # 7-segment LED display1, Segment E
NET "segm_lo(5)"       LOC =  D10; # 7-segment LED display1, Segment F
NET "segm_lo(6)"       LOC =  C10; # 7-segment LED display1, Segment G
NET "segm_hi(0)"       LOC =  B9 ; # 7-segment LED display2, Segment A
NET "segm_hi(1)"       LOC =  A8 ; # 7-segment LED display2, Segment B
NET "segm_hi(2)"       LOC =  B8 ; # 7-segment LED display2, Segment C
NET "segm_hi(3)"       LOC =  E7 ; # 7-segment LED display2, Segment D
NET "segm_hi(4)"       LOC =  E8 ; # 7-segment LED display2, Segment E
NET "segm_hi(5)"       LOC =  E10; # 7-segment LED display2, Segment F
NET "segm_hi(6)"       LOC =  E9 ; # 7-segment LED display2, Segment G

# User LED (active high)
NET "dsuact"             LOC =  A9 ; # User LED

# User push button switches (SW5, SW6)
NET "dsubre"           LOC =  D7 ; # User Push Button Switch Input 1 (SW5)
NET "btn_2"           LOC =  A6 ; # User Push Button Switch Input 2 (SW6)

# User DIP switch (SW2)
# They are sorted from left to right as DIP(0)..DIP(7)
NET "dip(0)"          LOC =  B4 ; # User Switch Input 1
NET "dip(1)"          LOC =  A4 ; # User Switch Input 2
NET "dip(2)"          LOC =  C4 ; # User Switch Input 3
NET "dip(3)"          LOC =  C5 ; # User Switch Input 4
NET "dip(4)"          LOC =  B5 ; # User Switch Input 5
NET "dip(5)"          LOC =  A5 ; # User Switch Input 6
NET "dip(6)"          LOC =  D6 ; # User Switch Input 7
NET "dip(7)"          LOC =  C6 ; # User Switch Input 8

# RS232 Port
NET "dsurx"       LOC =  B7 ; # Received Data, RD to DB9 (pin 2)   - From the PC side ( send data from FPGA )
NET "dsutx"       LOC =  A7 ; # Transmit Data, TD from DB9 (pin 3) - 

# Virtex-II VBAT
NET "vbat"            LOC =  A21; # VBAT input pin - connected to 3.3V through the JP15

# LVDS Port Signals
# - Transmit port
#NET "lvds_out_1n"     LOC =  H2 ; # Negative Data Transmit Bit 1 (J4 - pin 1)
#NET "lvds_out_1p"     LOC =  H1 ; # Positive Data Transmit Bit 1 (J4 - pin 2)
#NET "lvds_out_2n"     LOC =  J2 ; # Negative Data Transmit Bit 2 (J4 - pin 3)
#NET "lvds_out_2p"     LOC =  J1 ; # Positive Data Transmit Bit 2 (J4 - pin 4)
#NET "lvds_out_3n"     LOC =  K2 ; # Negative Data Transmit Bit 3 (J4 - pin 5)
#NET "lvds_out_3p"     LOC =  K1 ; # Positive Data Transmit Bit 3 (J4 - pin 6)
#NET "lvds_out_4n"     LOC =  E4 ; # Negative Data Transmit Bit 4 (J4 - pin 7)
#NET "lvds_out_4p"     LOC =  E3 ; # Positive Data Transmit Bit 4 (J4 - pin 8)
#NET "lvds_out_5n"     LOC =  F4 ; # Negative Data Transmit Bit 5 (J4 - pin 11)
#NET "lvds_out_5p"     LOC =  F3 ; # Positive Data Transmit Bit 5 (J4 - pin 12)
#NET "lvds_out_6n"     LOC =  G4 ; # Negative Data Transmit Bit 6 (J4 - pin 13)
#NET "lvds_out_6p"     LOC =  G3 ; # Positive Data Transmit Bit 6 (J4 - pin 14)
#NET "lvds_out_7n"     LOC =  H4 ; # Negative Data Transmit Bit 7 (J4 - pin 15)
#NET "lvds_out_7p"     LOC =  H3 ; # Positive Data Transmit Bit 7 (J4 - pin 16)
#NET "lvds_out_8n"     LOC =  J4 ; # Negative Data Transmit Bit 8 (J4 - pin 17)
#NET "lvds_out_8p"     LOC =  J3 ; # Positive Data Transmit Bit 8 (J4 - pin 18)
#NET "lvds_out_9n"     LOC =  K4 ; # Negative Data Transmit Bit 9 (J4 - pin 21)
#NET "lvds_out_9p"     LOC =  K3 ; # Positive Data Transmit Bit 9 (J4 - pin 22)
#NET "lvds_out_10n"    LOC =  L3 ; # Negative Data Transmit Bit 10 (J4 - pin 23)
#NET "lvds_out_10p"    LOC =  L2 ; # Positive Data Transmit Bit 10 (J4 - pin 24)
#NET "lvds_out_11n"    LOC =  L5 ; # Negative Data Transmit Bit 11 (J4 - pin 25)
#NET "lvds_out_11p"    LOC =  L4 ; # Positive Data Transmit Bit 11 (J4 - pin 26)
#NET "lvds_out_12n"    LOC =  E6 ; # Negative Data Transmit Bit 12 (J4 - pin 27)
#NET "lvds_out_12p"    LOC =  E5 ; # Positive Data Transmit Bit 12 (J4 - pin 28)
#NET "lvds_out_13n"    LOC =  F5 ; # Negative Data Transmit Bit 13 (J4 - pin 31)
#NET "lvds_out_13p"    LOC =  G5 ; # Positive Data Transmit Bit 13 (J4 - pin 32)
#NET "lvds_out_14n"    LOC =  H5 ; # Negative Data Transmit Bit 14 (J4 - pin 33)
#NET "lvds_out_14p"    LOC =  J6 ; # Positive Data Transmit Bit 14 (J4 - pin 34)
#NET "lvds_out_15n"    LOC =  J5 ; # Negative Data Transmit Bit 15 (J4 - pin 35)
#NET "lvds_out_15p"    LOC =  K5 ; # Positive Data Transmit Bit 15 (J4 - pin 36)
#NET "lvds_out_16n"    LOC =  K6 ; # Negative Data Transmit Bit 16 (J4 - pin 37)
#NET "lvds_out_16p"    LOC =  L6 ; # Positive Data Transmit Bit 16 (J4 - pin 38)
## - Receive port
#NET "lvds_in_1p"     LOC =  M2 ; # Positive Data Receive Bit 1 (J6 - pin 3)
#NET "lvds_in_1n"     LOC =  M1 ; # Negative Data Receive Bit 1 (J6 - pin 4)
#NET "lvds_in_2p"     LOC =  N2 ; # Positive Data Receive Bit 2 (J6 - pin 5)
#NET "lvds_in_2n"     LOC =  N1 ; # Negative Data Receive Bit 2 (J6 - pin 6)
#NET "lvds_in_3p"     LOC =  P2 ; # Positive Data Receive Bit 3 (J6 - pin 7)
#NET "lvds_in_3n"     LOC =  P1 ; # Negative Data Receive Bit 3 (J6 - pin 8)
#NET "lvds_in_4p"     LOC =  R2 ; # Positive Data Receive Bit 4 (J6 - pin 9)
#NET "lvds_in_4n"     LOC =  R1 ; # Negative Data Receive Bit 4 (J6 - pin 10)
#NET "lvds_in_5p"     LOC =  T2 ; # Positive Data Receive Bit 5 (J6 - pin 13)
#NET "lvds_in_5n"     LOC =  T1 ; # Negative Data Receive Bit 5 (J6 - pin 14)
#NET "lvds_in_6p"     LOC =  U2 ; # Positive Data Receive Bit 6 (J6 - pin 15)
#NET "lvds_in_6n"     LOC =  U1 ; # Negative Data Receive Bit 6 (J6 - pin 16)
#NET "lvds_in_7p"     LOC =  V2 ; # Positive Data Receive Bit 7 (J6 - pin 17)
#NET "lvds_in_7n"     LOC =  V1 ; # Negative Data Receive Bit 7 (J6 - pin 18)
#NET "lvds_in_8p"     LOC =  W2 ; # Positive Data Receive Bit 8 (J6 - pin 19)
#NET "lvds_in_8n"     LOC =  W1 ; # Negative Data Receive Bit 8 (J6 - pin 20)
#NET "lvds_in_9p"     LOC =  Y2 ; # Positive Data Receive Bit 9 (J6 - pin 23)
#NET "lvds_in_9n"     LOC =  Y1 ; # Negative Data Receive Bit 9 (J6 - pin 24)
#NET "lvds_in_10p"    LOC =  M6 ; # Positive Data Receive Bit 10 (J6 - pin 25)
#NET "lvds_in_10n"    LOC =  M5 ; # Negative Data Receive Bit 10 (J6 - pin 26)
#NET "lvds_in_11p"    LOC =  M4 ; # Positive Data Receive Bit 11 (J6 - pin 27)
#NET "lvds_in_11n"    LOC =  M3 ; # Negative Data Receive Bit 11 (J6 - pin 28)
#NET "lvds_in_12p"    LOC =  N4 ; # Positive Data Receive Bit 12 (J6 - pin 29)
#NET "lvds_in_12n"    LOC =  N3 ; # Negative Data Receive Bit 12 (J6 - pin 30)
#NET "lvds_in_13p"    LOC =  P4 ; # Positive Data Receive Bit 13 (J6 - pin 33)
#NET "lvds_in_13n"    LOC =  P3 ; # Negative Data Receive Bit 13 (J6 - pin 34)
#NET "lvds_in_14p"    LOC =  R4 ; # Positive Data Receive Bit 14 (J6 - pin 35)
#NET "lvds_in_14n"    LOC =  R3 ; # Negative Data Receive Bit 14 (J6 - pin 36)
#NET "lvds_in_15p"    LOC =  T4 ; # Positive Data Receive Bit 15 (J6 - pin 37)
#NET "lvds_in_15n"    LOC =  T3 ; # Negative Data Receive Bit 15 (J6 - pin 38)
#NET "lvds_in_16p"    LOC =  U4 ; # Positive Data Receive Bit 16 (J6 - pin 39)
#NET "lvds_in_16n"    LOC =  U3 ; # Negative Data Receive Bit 16 (J6 - pin 40)
## - Transmit control port
#NET "lvds_out_clkp"  LOC =  C1 ; # Positive Transmit Clock (J7 - pin 1)
#NET "lvds_out_clkn"  LOC =  C2 ; # Negative Transmit Clock (J7 - pin 2)
#NET "lvds_out_sclkp" LOC =  D1 ; # Positive Transmit Status Clock (J7 - pin 5)
#NET "lvds_out_sclkn" LOC =  D2 ; # Negative Transmit Status Clock (J7 - pin 6)
#NET "lvds_out_st_1p" LOC =  E1 ; # Positive Transmit Status 1 (J7 - pin 9)
#NET "lvds_out_st_1n" LOC =  E2 ; # Negative Transmit Status 1 (J7 - pin 10)
#NET "lvds_out_st_2p" LOC =  F1 ; # Positive Transmit Status 2 (J7 - pin 11)
#NET "lvds_out_st_2n" LOC =  F2 ; # Negative Transmit Status 2 (J7 - pin 12)
#NET "lvds_out_ctrlp" LOC =  G1 ; # Positive Transmit Control (J7 - pin 13)
#NET "lvds_out_ctrln" LOC =  G2 ; # Negative Transmit Control (J7 - pin 14)
## - Receive control port
#NET "lvds_in_ctrln" LOC =  V3 ; # Negative Receive Control (J8 - pin 1)
#NET "lvds_in_ctrlp" LOC =  V4 ; # Positive Receive Control (J8 - pin 2)
#NET "lvds_in_st_2n" LOC =  N5 ; # Negative Receive Status 2 (J8 - pin 3)
#NET "lvds_in_st_2p" LOC =  N6 ; # Positive Receive Status 2 (J8 - pin 4)
#NET "lvds_in_st_1n" LOC =  P5 ; # Negative Receive Status 1 (J8 - pin 5)
#NET "lvds_in_st_1p" LOC =  P6 ; # Positive Receive Status 1 (J8 - pin 6)
#NET "lvds_in_sclkn" LOC =  W11; # Negative Receive Status Clock (J8 - pin 9)
#NET "lvds_in_sclkp" LOC =  V11; # Positive Receive Status Clock (J8 - pin 10)
#NET "lvds_in_clkn"  LOC = AA11; # Negative Receive Clock (J8 - pin 13)
#NET "lvds_in_clkp"  LOC =  Y11; # Positive Receive Clock (J8 - pin 14)
#
## P160 Expansion Module Connectors
## JX1 User I/O Connector
#NET "jx1_a1"  LOC =  C19; # JX1 pin A1 - TCK
#NET "jx1_a3"  LOC =  B20; # JX1 pin A3 - TMS
#NET "jx1_a9"  LOC =  K22; # JX1 pin A9 - LIOA9
#NET "jx1_a11" LOC =  J21; # JX1 pin A11 - LIOA11
#NET "jx1_a13" LOC =  G22; # JX1 pin A13 - LIOA13
#NET "jx1_a15" LOC =  F21; # JX1 pin A15 - LIOA15
#NET "jx1_a17" LOC =  D22; # JX1 pin A17 - LIOA17
#NET "jx1_a19" LOC =  C21; # JX1 pin A19 - LIOA19
#NET "jx1_a21" LOC =  L20; # JX1 pin A21 - LIOA21
#NET "jx1_a23" LOC =  K19; # JX1 pin A23 - LIOA23
#NET "jx1_a25" LOC =  H20; # JX1 pin A25 - LIOA25
#NET "jx1_a27" LOC =  G19; # JX1 pin A27 - LIOA27