代码搜索结果
找到约 10,000 项符合
FPGA 的代码
fifo存储器举例：(注3).txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fifo.txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
d.vhd
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fifo存储器举例：(注3).txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
ram.xco
# BEGIN Project Options
SET flowvendor = Other
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = D:\Develop\PQS\FPGA\fft_test\fft_test_core\tmp
SET speedgrade = -5
SET simulationfiles =
fifo存储器举例：(注3).txt
-- A First-in First-out Memory
-- a first-in first out memory, uses a synchronising clock
-- generics allow fifos of different sizes to be instantiated
-- download from: www.fpga.com.cn & www.pld.c
fpgalutabsolutemapping.java~
/*
* FPGALUTMapping.java
*
* Created on 17 July 2003, 20:34
*/
package es.pj.circuits.fpgaft;
import es.BitSet;
import es.pj.circuits.*;
/** FPGA LUT Structure is composed of CLBs containing
fpgalutabsolutemapping_1.java~
/*
* FPGALUTMapping.java
*
* Created on 17 July 2003, 20:34
*/
package es.pj.circuits.fpgaft;
import es.BitSet;
import es.pj.circuits.*;
/** FPGA LUT Structure is composed of CLBs containing
fpgalutabsolutemapping.java
/*
* FPGALUTMapping.java
*
* Created on 17 July 2003, 20:34
*/
package jaga.pj.circuits.fpgaft;
import jaga.BitSet;
import jaga.pj.circuits.*;
/** FPGA LUT Structure is composed of CLBs cont
fpgalutvariablesizedabsolutemapping.java~
/*
* FPGALUTMapping.java
*
* Created on 17 July 2003, 20:34
*/
package es.pj.circuits.fpgaft;
import es.BitSet;
import es.pj.circuits.*;
/** FPGA LUT Structure is composed of CLBs containing