fpgalutvariablesizedabsolutemapping.java~

Java遗传算法库

/*
 * FPGALUTMapping.java
 *
 * Created on 17 July 2003, 20:34
 */

package es.pj.circuits.fpgaft;

import es.BitSet;
import es.pj.circuits.*;

/** <p>FPGA LUT Structure is composed of CLBs containing a LUT and an Edge Triggered D-Latch.
 * The Variable Sized mapping differs mainly from the fixed size in that inputs are defined as addresses 0,1...nrIns -1.
 * Genotype structure:
 *First nrOuts * ( bitsPerVar + 1 ) define where to get outputs from, ala VassilevMapping.<p>
 *The rest is divided into genes composed of three sections:<p>
 *<t>First 2^LUTInputs bits for the Look-Up Table. <p>
 *<t>Next LUTInputs * ( bitsPerVar + 1 ) bits define where to get inputs of LUT from. <p>
 *<t> Next bitsPerVar+1 bits define the input of the Latch. <p>
 *
 * @author  mmg20
 */
public class FPGALUTVariableSizedAbsoluteMapping implements CircuitMapping {
    
    protected int nrIns, nrOuts, nrLUTIns, bitsPerVar;
    protected ElementDelayModel delayModel;
    
    /** Creates a new instance of FPGALUTMapping 
      * @param ins Number of Inputs to Circuit NOT including the Clock for the Latches.
     * @param outs Number of Outputs to Circuit.
     * @param lutIns Number of Inputs to Look-Up Tables.
     * @param bpv Bits Per Variable, defines how many addressable CLBs there will be = 2^bpv-nrIns.
     * @param delMod The generator of delay values.
     */
    public FPGALUTVariableSizedAbsoluteMapping(int ins, int outs, int bpv, int lutIns, ElementDelayModel delMod) {
        nrIns = ins;
        nrOuts = outs;
        nrLUTIns = lutIns;
        bitsPerVar = bpv;
        delayModel = delMod;
    }
    
    /** Takes and individual and an array of arrays of logic elements where this
     * individual must be instantiated.
     * @param individual The individual to be mapped into a circuit.
     * @return Array consisting of three subarrays: The first will represent
     * the inputs to the circuit and is where the inputs will be fed in.  The second
     * represents the elements that are the outputs of the circuit and is where they
     * will be read out from.  The last is an array with all the elements of the
     * circuit.
     */
    public SimulatorLogicElement[][] map(BitSet individual) {        
        //System.out.println( individual ); //D
        int totalIns = nrIns; //  Clock is last one
        int bitsPerAdd = bitsPerVar + 1; // extra bit saying if LUT or Latch
        int LUTSize = 1 << nrLUTIns;
        int geneSize = LUTSize + ( nrLUTIns + 1 ) * bitsPerAdd; // One for D-Latch input
        int outputDefBlockSize = bitsPerAdd  * nrOuts;
        int nrDefinedCLBs = ( individual.length() - outputDefBlockSize ) / geneSize;
        nrDefinedCLBs = Math.max( 1, nrDefinedCLBs );
        int nrAddUnits = 1 << bitsPerAdd;
        
        SimulatorLogicElement[] inputs = new SimulatorLogicElement[ totalIns ];
        SimulatorLogicElement[] outputs = new SimulatorLogicElement[ nrOuts ];
        SimulatorFaultyDelayLE[] elements = new SimulatorFaultyDelayLE[ nrAddUnits ]; // for LUTs and Latches
        
        int latchIndexOffset = 1 << bitsPerVar;
        //int nrCLBs = latchIndexOffset - totalIns;
        
        
        // 1 - Create inputs
        for( int il = 0; il < totalIns; il++ )
        {
            elements[ il ] = new SimulatorFaultyDelayLE( 0 );
            elements[ latchIndexOffset + il ] = elements[ il ];
            inputs[ il ] = elements[ il ];
        }
        SimulatorFaultyDelayLE clockInput = new SimulatorFaultyDelayLE( 0 );

        // 2 - Create LUTs and Latches
        for( int cll = 0; cll < nrDefinedCLBs; cll++ )
        {
            elements[ totalIns + cll ] = new SimulatorLUT( individual.getBooleanChunk( outputDefBlockSize  + cll * geneSize, LUTSize ), delayModel.getDelay() );
            elements[ latchIndexOffset + totalIns + cll ] = new SimulatorEdgeDLatch( delayModel.getDelay() );
        }
        
        // 2.1 - Create Re-Mapping of CLBs and Latches outside range
        for( int cll = 0; cll < latchIndexOffset - nrDefinedCLBs - totalIns; cll++ )
        {
            elements[ nrDefinedCLBs + totalIns + cll ] = elements[ cll ];
            elements[ latchIndexOffset + nrDefinedCLBs + totalIns + cll ] = elements[ latchIndexOffset + cll ];
        }
                
        // 3 - Connect & Collapse all elements without inputs into single array
        SimulatorFaultyDelayLE[] onlyCLBs = new SimulatorFaultyDelayLE[ 2 * nrDefinedCLBs ];
        int genPos = outputDefBlockSize;
        for( int cll = 0; cll < nrDefinedCLBs; cll++ )
        {
            // 3.1 LUT
            SimulatorLogicElement[] LUTConn = new SimulatorLogicElement[ nrLUTIns ];
            genPos += LUTSize;
            for( int il = 0; il < nrLUTIns; il++ )
            {
                int iix = individual.bitsToInt( genPos, genPos + bitsPerAdd );
                LUTConn[ il ] = elements[ iix ];
                genPos += bitsPerAdd;
            }
            elements[ totalIns + cll ].connect( LUTConn );
            onlyCLBs[ cll ] = elements[ totalIns + cll ];
            
            // 3.2 Latch
            SimulatorLogicElement[] EDLConn = new SimulatorLogicElement[ 2 ];
            int iix = individual.bitsToInt( genPos, genPos + bitsPerAdd );
            EDLConn[ SimulatorEdgeDLatch.C ] = clockInput;
            EDLConn[ SimulatorEdgeDLatch.D ] = elements[ iix ];
            elements[ latchIndexOffset + totalIns + cll ].connect( EDLConn );
            genPos += bitsPerAdd;
            onlyCLBs[ nrDefinedCLBs + cll ] = elements[ latchIndexOffset + totalIns + cll ];
        }
        
        // 5. Connect Outs
        for( int ol = 0; ol < nrOuts; ol++ )
        {
            int currOut = individual.bitsToInt( ol * bitsPerAdd, ( ol + 1 ) * bitsPerAdd);
            outputs[ ol ] = elements[ currOut ];
        }
        
        // 6. Connect Clock
        inputs[ totalIns - 1 ] = elements[ totalIns - 1 ] = clockInput;
        
        // Debug - Print out everything in els and codes
        /*
        for( int el = 0; el < elements.length; el++ ) //onlyCLBs
        {
            SimulatorLogicElement currEl = elements[ el ];//onlyCLBs
            String story = "el " + el + "=" + currEl;
            if( currEl == null )
            {
                story += "null";
            }else
            {
                SimulatorLogicElement[] currCons = currEl.getInputs();
                if( currCons == null )
                {
                    story += "unCon";
                }else
                {
                    for( int il = 0; il < currCons.length; il++ )
                    {
                        story += " in" + il + "p=" + es.ESLib.indexOf( currCons[ il ], elements );
                    }
                }
            }
            System.out.println( story );
        }*/
        
        SimulatorLogicElement[][] rv = { inputs, outputs, onlyCLBs };
        return rv;
    }
    
    public void resetDelays(Object delayDef) {
        delayModel.set( delayDef );
    }
    
    public String toString()
    {
        String rv = "FPGALUTVariableSizedAbsoluteMapping with:";
        rv += "\n      # inputs = " + nrIns;
        rv += "\n      # outputs = " + nrOuts;
        rv += "\n      Bits per Variable = " + bitsPerVar;
        rv += "\n      # LUT inputs = " + nrLUTIns;
        rv += "\n      Delay Model: " + delayModel;
        return rv;
    }
    
    public SimulatorLogicElement getElementFromAddress(SimulatorLogicElement[][] inoutels, int address) {
        int latchOffset = ( 1 << bitsPerVar );
        boolean latch = ( address > latchOffset );
        if( latch )
        {
            address -= latchOffset;
        }
        if( address < nrIns )
        {
            return inoutels[ INPUTS ][ address ];
        }else
        {
            int newLatchOffset = inoutels[ ELEMENTS ].length / 2;
            int newAddress = address - nrIns;
            if( latch )
            {
                newAddress += newLatchOffset;
            }
            return inoutels[ ELEMENTS ][ newAddress ];
        }
    }    
    
}