ram.xco

用vhdl编写的FFT的代码,很全,很强大.

# BEGIN Project Options
SET flowvendor = Other
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = D:\Develop\PQS\FPGA\fft_test\fft_test_core\tmp
SET speedgrade = -5
SET simulationfiles = Behavioral
SET asysymbol = False
SET addpads = False
SET device = xc3s500e
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = cp132
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan3e
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET handshaking_pins=false
CSET init_value=0
CSET coefficient_file=D:\Develop\PQS\FPGA\fft_test\sin_tab_init.coe
CSET select_primitive=16kx1
CSET initialization_pin_polarity=Active_High
CSET global_init_value=0
CSET depth=128
CSET write_enable_polarity=Active_High
CSET port_configuration=Read_And_Write
CSET enable_pin_polarity=Active_High
CSET component_name=ram
CSET active_clock_edge=Rising_Edge_Triggered
CSET additional_output_pipe_stages=0
CSET disable_warning_messages=true
CSET limit_data_pitch=18
CSET primitive_selection=Optimize_For_Area
CSET enable_pin=false
CSET init_pin=false
CSET write_mode=Read_After_Write
CSET has_limit_data_pitch=false
CSET load_init_file=true
CSET width=16
CSET register_inputs=false
# END Parameters
GENERATE