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FPGA 的代码
简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
jtag.c
// JTAG parallel cable demo code
// (c) fpga4fun.com KNJN LLC 2006
// This code assumes that you have a JTAG parallel cable connected to your PC
// Works with Xilinx parallel III or Altera ByteBl
简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
changefreq.mac
INCLUDE regClock.inc
INCLUDE regBase.inc
; cpld register address define
FPGA_REGS_BASE_PHYSICAL EQU (0x08000000)
JSSR_OFFSET EQU (0x20)
;---------------------------------------
ch15.6.htm
15.6 FPGA Partitioning