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<P>[ <A HREF="CH15.htm">Chapter start</A> ] [ <A HREF="CH15.5.htm">Previous page</A> ] [ <A HREF="CH15.7.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
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15.6 <A NAME="41758">
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FPGA Partitioning</H1>
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In <A HREF="CH15.3.htm#41516" CLASS="XRef">
Section 15.3</A>
we saw how many different issues have to be considered when partitioning a complex system into custom ASICs. There are no commercial tools that can help us with all of these issues—a spreadsheet is the best tool in this case. Things are a little easier if we limit ourselves to partitioning a group of logic cells into FPGAs—and restrict the FPGAs to be all of the same type.</P>
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15.6.1 ATM Simulator</H2>
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In this section we shall examine a hardware simulator for <A NAME="marker=175712">
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Asynchronous Transfer Mode (<A NAME="marker=175714">
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ATM<A NAME="marker=183703">
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). ATM is a signaling protocol for many different types of traffic including constant bit rates (voice signals) as well as variable bit rates (compressed video). The ATM Connection Simulator is a card that is connected to a computer. Under computer control the card monitors and corrupts the ATM signals to simulate the effects of real networks. An example would be to test different video compression algorithms. Compressed video is very bursty (brief periods of very high activity), has very strict delay constraints, and is susceptible to errors. ATM is based on ATM cells (packets). Each ATM cell has 53 bytes: a 5-byte header and a 48-byte payload; <A HREF="CH15.6.htm#16959" CLASS="XRef">
Figure 15.4</A>
shows the format of the ATM packet. The ATM Connection Simulator looks at the entire header as an address.</P>
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FIGURE 15.4 <A NAME="16959">
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The asynchronous transfer mode (ATM) cell format. The ATM protocol uses 53-byte cells or packets of information with a data payload and header information for routing and error control.</P>
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<A HREF="CH15.6.htm#11762" CLASS="XRef">
Figure 15.5</A>
shows the system block diagram of the ATM simulator designed by Craig Fujikami at the University of Hawaii. Now produced by AdTech, the simulator emulates the characteristics of a single connection in an ATM network and models ATM traffic policing, ATM cell delays, and ATM cell errors. The simulator is partitioned into the three major blocks, shown in <A HREF="CH15.6.htm#11762" CLASS="XRef">
Figure 15.5</A>
, and connected to an IBM-compatible PC through an Intel 80186 controller board together with an interface board. These three blocks are</P>
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FIGURE 15.5 <A NAME="11762">
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An asynchronous transfer mode (ATM) connection simulator.</P>
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<UL>
<LI CLASS="BulletFirst">
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The traffic policer, which regulates the input to the simulator.</LI>
<LI CLASS="BulletList">
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The delay generator, which delays ATM cells, reorders ATM cells, and inserts ATM cells with valid ATM cell headers.</LI>
<LI CLASS="BulletLast">
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The error generator, which produces bit errors and four random variables that are needed by the other two blocks.</LI>
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The error generator performs the following operations on ATM cells:</P>
<OL>
<LI CLASS="NumberFirst">
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Payload bit error ratio generation. The user specifies the Bernoulli probability, <SPAN CLASS="EquationVariables">
p</SPAN>
<SUB CLASS="Subscript">
BER</SUB>
, of the payload bit error ratio.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=90139">
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Random-variable generation for ATM cell loss, misinsertion, reordering, and deletion. </LI>
</OL>
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The delay generator delays, misinserts, and reorders the target ATM cells. Finally, the traffic policer performs the following operations:</P>
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Performs header screening and remapping. </LI>
<LI CLASS="NumberList">
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Checks ATM cell conformance.</LI>
<LI CLASS="NumberList">
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Deletes selected ATM cells.</LI>
</OL>
<P CLASS="Body">
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<A HREF="CH15.6.htm#22781" CLASS="XRef">
Table 15.7</A>
shows the partitioning of the ATM board into 12 Lattice Logic FPGAs (ispLSI 1048) corresponding to the 12 blocks shown in <A HREF="CH15.6.htm#11762" CLASS="XRef">
Figure 15.5</A>
. The Lattice Logic ispLSI 1048 has 48 GLBs (generic logic blocks) on each chip. This system was partitioned by hand—with difficulty. Tools for automatic partitioning of systems like this will become increasingly important. In <A HREF="CH15.6.htm#31500" CLASS="XRef">
Section 15.6.2</A>
we shall briefly look at some examples of such tools, before examining the partitioning methods that are used in <A HREF="CH15.7.htm#29058" CLASS="XRef">
Section 15.7</A>
. </P>
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TABLE 15.7 <A NAME="22781">
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Partitioning of the ATM board using Lattice Logic ispLSI 1048 FPGAs. Each FPGA contains 48 generic logic blocks (GLBs).</P>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
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Chip #</P>
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<P CLASS="TableLeft">
<A NAME="pgfId=144148">
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<SPAN CLASS="TableHeads">
Size</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=144278">
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Chip #</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=175806">
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</P>
</TD>
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<P CLASS="TableLeft">
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</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=185346">
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<SPAN CLASS="TableHeads">
Size</SPAN>
</P>
</TD>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=144154">
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1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=144156">
</A>
42 GLBs</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=144282">
</A>
7</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=175808">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=175824">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=144284">
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36 GLBs</P>
</TD>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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2</P>
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<A NAME="pgfId=144164">
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64 k-bit <SPAN CLASS="Symbol">
¥</SPAN>
8 SRAM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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8</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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22 GLBs</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=144172">
</A>
38 GLBs</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=144290">
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9</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=175812">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=175828">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=144292">
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256 k-bit <SPAN CLASS="Symbol">
¥</SPAN>
16 SRAM</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=144178">
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4</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=144180">
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38 GLBs</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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10</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=175814">
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</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=175830">
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</P>
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<TD ROWSPAN="1" COLSPAN="1">
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43 GLBs</P>
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<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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5</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
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42 GLBs</P>
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<TD ROWSPAN="1" COLSPAN="1">
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11</P>
</TD>
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<P CLASS="Table">
<A NAME="pgfId=175816">
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</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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</P>
</TD>
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40 GLBs</P>
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6</P>
</TD>
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<P CLASS="TableLeft">
<A NAME="pgfId=144252">
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64 k-bit <SPAN CLASS="Symbol">
¥</SPAN>
16 SRAM</P>
</TD>
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12</P>
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</P>
</TD>
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<P CLASS="TableLast">
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</P>
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30 GLBs</P>
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</DIV>
<DIV>
<H2 CLASS="Heading2">
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15.6.2 <A NAME="31500">
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Automatic Partitioning with FPGAs</H2>
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Some vendors of programmable ASICs provide partitioning software. For example, Altera uses its own software system for design. You can perform design entry using an HDL, schematic entry, or using the Altera hardware design language (AHDL)—similar to PALASM or ABEL. In AHDL you can direct the partitioner to automatically partition logic into chips within the same family, using the <A NAME="marker=147253">
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AUTO keyword:</P>
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DEVICE top_level IS AUTO; % the partitioner assign logic</P>
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You can use the <SPAN CLASS="BodyComputer">
CLIQUE</SPAN>
<A NAME="marker=32730">
</A>
keyword to keep logic together (this is not quite the same as a clique in a graph—more on this in <A HREF="CH15.7.htm#20759" CLASS="XRef">
Section 15.7.3</A>
):</P>
<P CLASS="ComputerFirst">
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CLIQUE fast_logic</P>
<P CLASS="Computer">
<A NAME="pgfId=32668">
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BEGIN</P>
<P CLASS="Computer">
<A NAME="pgfId=32669">
</A>
|shift_register: MACRO; % keep this in one device</P>
<P CLASS="ComputerLast">
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END;</P>
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An additional option, to reserve space on a device, is very useful for making last minute additions or changes.</P>
</DIV>
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