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-- A Variety of Adder Styles -- download from: www.fpga.com.cn & www.pld.com.cn ------------------------------------------------------------------------ -- Single-bit adder -----------------------

//==================================================================== // // copyright (c) 2007, Hisilicon Technologies Co.,Ltd // All rights reserved. // // IP LIB INDEX: HIAVD FPGA // IP Name

f "noname"; #file 0 f "noname"; #file 1 f "d:\synplicity\fpga_81\lib\vhd\std.vhd"; #file 2 f "e:\modelsim\vr_fifo\src\vr_fifo_rtl.vhd"; #file 3 f "d:\synplicity\fpga_81\lib\vhd\std1164.vhd"; #file

PROMGEN: Xilinx Prom Generator G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. promgen -w -p mcs -c FF -o g:\girija\fpga\bcd_7seg//bcd -u 0 G:\GIRIJA\FPGA\bcd_7seg\bcd_7seg_cclktemp

f "noname"; #file 0 f "d:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1 f "d:\eda\synplicity\fpga_81\bin\..\lib\xilinx\unisim.v"; #file 2 f "e:\ise_prj\emif_com\emif_com.v"; #file 3 VNAME '

vendor_name = ModelSim source_file = 1, D:/fpga例子/ram_256/ram_256.vhd source_file = 1, D:/fpga例子/ram_256/ram_256.vwf design_name = ram_256 instance = comp, \we~I\, we, ram_256, 1 instance = comp,

|mcu_sram_test adstart mcu_fpga_control:inst8.clk clk => sram_control:inst4.clk clk => osc:inst2.clk clk => mfreq:freq8.clk_in wr => mcu_fpga_control:inst8.

f "noname"; #file 0 f "d:\program files\synplicity\fpga_81\lib\vhd\std.vhd"; #file 1 f "d:\vhdl_exercise\add_full_n\add_full_n.vhd"; #file 2 f "d:\program files\synplicity\fpga_81\lib\vhd\std1164.v

f "noname"; #file 0 f "noname"; #file 1 f "d:\program files\synplicity\fpga_81\lib\vhd\std.vhd"; #file 2 f "e:\vhdl\f8051\mc8051_p.vhd"; #file 3 f "d:\program files\synplicity\fpga_81\lib\vhd\std1

f "noname"; #file 0 f "noname"; #file 1 f "d:\program files\synplicity\fpga_81\lib\vhd\std.vhd"; #file 2 f "e:\vhdl\f8051\mc8051_p.vhd"; #file 3 f "d:\program files\synplicity\fpga_81\lib\vhd\std1