代码搜索结果

vendor_name = ModelSim source_file = 1, E:/My_Design/FPGA/Filter/Filter.vhd source_file = 1, E:/My_Design/FPGA/Filter/Filter.vwf design_name = Filter instance = comp, \fs_in~I\, fs_in, Filter, 1

#include "FPGA_Test.h" EX_INTERRUPT_HANDLER(SPORT1_TX_ISR_For_FPGA_Init) { static int TX_Number = 0; if(TX_Number < 1) { TX_Number = TX_Number + 1; *pFIO0_FLAG_C = 0xc800; ssy

f "noname"; #file 0 f "d:\program files\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1 f "d:\program files\synplicity\fpga_81\bin\..\lib\xilinx\unisim.v"; #file 2 f "f:\basys\basys\huanyizuoyi17\

f "noname"; #file 0 f "noname"; #file 1 f "c:\program files\synplicity\fpga_85\lib\xilinx\unisim.v"; #file 2 f "c:\program files\synplicity\fpga_85\bin\..\lib\xilinx\unisim.v"; #file 3 f "d:\devel

f "noname"; #file 0 f "d:\software\synplify 8.6.1\fpga_861\lib\xilinx\unisim.v"; #file 1 f "d:\software\synplify 8.6.1\fpga_861\bin\..\lib\xilinx\unisim.v"; #file 2 f "e:\homework\ise8.1 work\peopl

xst -intstyle ise -ifn __projnav/can_top.xst -ofn can_top.syr xst -intstyle ise -ifn __projnav/can_top.xst -ofn can_top.syr ngdbuild -intstyle ise -dd e:\program\fpga_program\for_fpga\can\ise\canbus

CommandLine-Map s CommandLine-Ngdbuild E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -intstyle ise -dd _ngo -nt

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\xst.exe -ise E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/DDR_TX_TEST.ise -intstyle ise -ifn E:/linpingping/ATCA_converge_board/DAC/L

set -tmpdir "E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/xst/projnav.tmp" set -xsthdpdir "E:/linpingping/ATCA_converge_board/DAC/LVDS_DDR_List_FPGA2/xst" run -ifn DDR_TX_TEST.prj -i

vendor_name = ModelSim source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/quartus/RAM_36.v source_file = 1, E:/farsight_fpga_course/code/high/onchip ram/quartus/ram_control.v source_file