people4.srd

这是我自己写的4人表决器源码

f "noname"; #file 0
f "d:\software\synplify 8.6.1\fpga_861\lib\xilinx\unisim.v"; #file 1
f "d:\software\synplify 8.6.1\fpga_861\bin\..\lib\xilinx\unisim.v"; #file 2
f "e:\homework\ise8.1 work\people4\people4.v"; #file 3
VNAME 'work.people4.verilog'; # view id 0
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