filter_modelsim.xrf

vhdl抗抖动滤波器的设计

vendor_name = ModelSim
source_file = 1, E:/My_Design/FPGA/Filter/Filter.vhd
source_file = 1, E:/My_Design/FPGA/Filter/Filter.vwf
design_name = Filter
instance = comp, \fs_in~I\, fs_in, Filter, 1
instance = comp, \clk~I\, clk, Filter, 1
instance = comp, \clk~clkctrl\, clk~clkctrl, Filter, 1
instance = comp, \cnt1~154\, cnt1~154, Filter, 1
instance = comp, \cnt1[1]\, cnt1[1], Filter, 1
instance = comp, \cnt1~152\, cnt1~152, Filter, 1
instance = comp, \cnt1[0]\, cnt1[0], Filter, 1
instance = comp, \cnt1~153\, cnt1~153, Filter, 1
instance = comp, \cnt1[2]\, cnt1[2], Filter, 1
instance = comp, \cnt1[0]~151\, cnt1[0]~151, Filter, 1
instance = comp, \cnt0~152\, cnt0~152, Filter, 1
instance = comp, \cnt0[1]\, cnt0[1], Filter, 1
instance = comp, \cnt0~150\, cnt0~150, Filter, 1
instance = comp, \cnt0[0]\, cnt0[0], Filter, 1
instance = comp, \cnt0~151\, cnt0~151, Filter, 1
instance = comp, \cnt0[2]\, cnt0[2], Filter, 1
instance = comp, \cnt0[0]~149\, cnt0[0]~149, Filter, 1
instance = comp, \fs_out~158\, fs_out~158, Filter, 1
instance = comp, \fs_out~reg0\, fs_out~reg0, Filter, 1
instance = comp, \fs_out~I\, fs_out, Filter, 1