代码搜索结果

set -tmpdir "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xst/projnav.tmp" set -xsthdpdir "E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xst" run -ifn lvds_bist_top.prj -i

CommandLine-Map s CommandLine-Ngdbuild E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -dd _ngo -nt time

CommandLine E:\FPGA\Xilinx\10.1\ISE\bin\nt\unwrapped\xst.exe -ise E:/linpingping/ATCA_converge_board/LVDS_Serdes_list_FPGA1/xapp860.ise -intstyle ise -ifn E:/linpingping/ATCA_converge_board/LVDS_Serde

quietly set ACTELLIBNAME proasic3 quietly set PROJECT_DIR "H:/fpga_test/fpga_fifo_0122_02" vlib presynth vmap proasic3 "$env(MODEL_TECH)/../actel/vlog/proasic3" vmap presynth presynth vlog "+incd

#-- Synplicity, Inc. #-- Version Synplify 8.8A1 #-- Project file H:\fpga_test\fpga_fifo_0122_02\synthesis\run_options.txt #-- Written on Wed May 07 16:22:43 2008 #add_file options add_file -v

E:/fpga/enter_x.v {1 {vlog -work work E:/fpga/enter_x.v Model Technology ModelSim SE vlog 6.0c Compiler 2005.02 Feb 2 2005 -- Compiling module enter_x Top level modules: enter_x } {} {}} E:

D:/整理资料/fpga/分频器/db/clkdiv.sim.vwf 6368812 11642352 390 5273540 0 D:/整理资料/fpga/分频器/clkdiv.vwf 102713432 106619682 597 3906250 0 clkdiv.vwf 0 0 0 0 0

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\stratix.v,

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\stratix.v,

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\cycloneii.v