state2.xrf

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vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify
source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\stratix.v, synplify
source_file = 3, c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v, synplify
source_file = 4, c:\eda\synplicity\fpga_81\lib\altera\altera_lpm.v, synplify
source_file = 5, c:\prj\example-6-1\fsm\state2\state2.v, synplify
design_name=state2
instance = port, nrst, , state2, 5, 13:15:13:18
instance = port, clk, , state2, 5, 13:20:13:22
instance = port, i1, , state2, 5, 14:15:14:16
instance = port, i2, , state2, 5, 14:18:14:19
instance = port, o1, , state2, 5, 15:15:15:16
instance = port, o2, , state2, 5, 15:18:15:19
instance = port, err, , state2, 5, 15:21:15:23
instance = comp, CS_1__Z, , state2, 5, 28:0:28:5
instance = comp, CS_0__Z, , state2, 5, 28:0:28:5
instance = comp, o2_x_cZ, , state2, 5, 36:6:36:7
instance = comp, err_0_x_cZ, , state2, 5, 36:6:36:7
instance = comp, err_x_cZ, , state2, 5, 36:6:36:7
instance = comp, i2_in, , state2, 5, 14:18:14:19
instance = comp, i1_in, , state2, 5, 14:15:14:16
instance = comp, clk_in, , state2, 5, 13:20:13:22
instance = comp, nrst_in, , state2, 5, 13:15:13:18
instance = comp, err_out, , state2, 5, 15:21:15:23
instance = comp, o2_out, , state2, 5, 15:18:15:19
instance = comp, o1_out, , state2, 5, 15:15:15:16
instance = comp, CS_3_0_, , state2, 5, 28:0:28:5