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runxst_tcl.rsp
set allSynthModules {serial.MOD diag.MOD fpga_40RS232.MOD}
runxst_tcl.rsp
set allSynthModules {serial.MOD diag.MOD fpga_40RS232.MOD}
netlist.lst
R:\training\training\desperf\labs\fpga_editor\correlate_and_accumulate.ngc 1132023826
OK
demo_all.mrp
Release 7.1.01i Map H.39
Xilinx Mapping Report File for Design 'demo_all'
Design Information
------------------
Command Line : E:/Program/EDA/Xilinx/bin/nt/map.exe -ise
e:\demo_fpga\DEMO_FPGA.ise
digital_clk.mrp
Release 7.1.01i Map H.39
Xilinx Mapping Report File for Design 'digital_clk'
Design Information
------------------
Command Line : E:/Program/EDA/Xilinx/bin/nt/map.exe -ise
e:\demo_fpga\DEMO_FPGA.i
qam16.srr
#Build: Synplify Pro 8.8.0.4, Build 008R, Dec 7 2006
#install: D:\Program\FPGA_software\Synplicity\fpga_8804
#OS: Windows XP 5.1
#Hostname: USER-73B7470377
#Implementation: 16QAM
#Tue Jun 24
updwloen.prj
Created by PCM: 3/5/102
Empty design C:\FPGA\UPDWLOEN\UPDWLOEN\updwloen.EDF created: 3/5/102 [15.18.31].
'' saved on 02/03/05 15:25
'C:\FPGA\UPDWLOEN\UPDWLOEN\UPDNLOEN.VHD' saved on 02/03/05 15:25
dev_io.plg
礦ision3 Build Log
Project:
F:\YCL-USB2.0-FPGA开发板V2.0\测试程序源代码（包括VC工程文件及Firmware,Verilog代码）\USB2.0+FPGA_EXAMPLES\USB_FPGA_IO测试\Firmware\DEV_IO.uv2
Project Fil
gh_fasm.vhd
---------------------------------------------------------------------
-- Filename: gh_fasm.vhd
--
--
-- Description:
-- FASM (FPGA and ASIC Subset Model)
-- Synchronous write port, Asynchro
adc_max186_sm.v
//*****************************************************************************************//
// Project : FPGA based Digital Design using Verilog HDL
// File : adc_max186_sm.v
/