📄 qam16.srr
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#Build: Synplify Pro 8.8.0.4, Build 008R, Dec 7 2006
#install: D:\Program\FPGA_software\Synplicity\fpga_8804
#OS: Windows XP 5.1
#Hostname: USER-73B7470377
#Implementation: 16QAM
#Tue Jun 24 09:48:14 2008
$ Start of Compile
#Tue Jun 24 09:48:14 2008
Synplicity Verilog Compiler, version 3.7, Build 192R, built Apr 11 2007
Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved
@I::"D:\Program\FPGA_software\Synplicity\fpga_8804\lib\xilinx\unisim.v"
@I::"E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\ddsqam.v"
@W: CS140 :"E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\ddsqam.v":51:4:51:4|black_box attribute has been renamed to syn_black_box. Change black_box usage to synthesis syn_black_box for upward compatibility.
@N: CG334 :"E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\ddsqam.v":60:12:60:24|Read directive translate_off
@N: CG333 :"E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\ddsqam.v":3172:12:3172:23|Read directive translate_on
@I::"E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\qam16.v"
Verilog syntax check successful!
Selecting top level module qam16
@N: CG364 :"E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\ddsqam.v":43:7:43:12|Synthesizing module ddsqam
@N: CG364 :"E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\qam16.v":22:7:22:11|Synthesizing module qam16
@N: CG179 :"E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\qam16.v":51:11:51:13|Removing redundant assignment
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jun 24 09:48:15 2008
###########################################################]
Synplicity Xilinx Technology Mapper, Version 8.8.0p, Build 069R, Built Apr 17 2007 19:41:05
Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved
Product Version Version 8.8.0.4
Reading constraint file: E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\qam16.sdc
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled
Reading Xilinx I/O pad type table from file <D:\Program\FPGA_software\Synplicity\fpga_8804\lib/xilinx/x_io_tbl.txt>
Reading Xilinx Rocket I/O parameter type table from file <D:\Program\FPGA_software\Synplicity\fpga_8804\lib/xilinx/gttype.txt>
@N: MT206 |Autoconstrain Mode is ON
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 46MB)
@N: FX339 :"e:\wangqiuju\study\researchproject\program_has_done\verilog\16pam\16qam\qam16.v":174:11:174:68|Found addmux in view:work.qam16(verilog) inst un12_y[17:0]
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
######### START OF GENERATED CLOCK OPTIMIZATION REPORT #########[
================================================================
Instance:Pin Generated Clock Optimization Status
================================================================
######### END OF GENERATED CLOCK OPTIMIZATION REPORT #########]
Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 44MB peak: 46MB)
Clock Buffers:
Inserting Clock buffer for port clk12p5MHz, TNM=clk12p5MHz
Inserting Clock buffer for port clk, TNM=clk
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 46MB peak: 46MB)
Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 45MB peak: 46MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.47ns 80 / 44
2 0h:00m:00s -0.47ns 80 / 44
3 0h:00m:00s -0.47ns 80 / 44
------------------------------------------------------------
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.31ns 75 / 44
2 0h:00m:00s -0.31ns 75 / 44
3 0h:00m:00s -0.31ns 75 / 44
Timing driven replication report
No replication required.
4 0h:00m:00s -0.31ns 75 / 44
5 0h:00m:00s -0.31ns 75 / 44
6 0h:00m:00s -0.31ns 75 / 44
------------------------------------------------------------
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:00s -0.44ns 75 / 44
2 0h:00m:00s -0.44ns 75 / 44
3 0h:00m:00s -0.44ns 75 / 44
Timing driven replication report
No replication required.
4 0h:00m:00s -0.44ns 75 / 44
5 0h:00m:01s -0.44ns 75 / 44
6 0h:00m:01s -0.44ns 75 / 44
------------------------------------------------------------
Net buffering Report for view:work.qam16(verilog):
No nets needed buffering.
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 45MB peak: 46MB)
@N: FX164 |The option to pack flops in the IOB has not been specified
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 45MB peak: 46MB)
Writing Analyst data base E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\qam16.srm
@N: BN225 |Writing default property annotation file E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\qam16.map.
Writing EDIF Netlist and constraint files
Reading Xilinx net attributes from file <D:\Program\FPGA_software\Synplicity\fpga_8804\lib/xilinx/netattr.txt>
Version 8.8.0.4
Found clock qam16|clk with period 1.11ns
Found clock qam16|clk12p5MHz with period 1.25ns
@W: MT246 |Blackbox ddsqam is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jun 24 09:48:19 2008
#
Top view: qam16
Requested Frequency: 802.7 MHz
Wire load mode: top
Paths requested: 0
Constraint File(s): E:\wangqiuju\study\researchproject\program_has_done\VERILOG\16pam\16QAM\qam16.sdc
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..
Performance Summary
*******************
Worst slack in design: -0.852
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
--------------------------------------------------------------------------------------------------------------------------
qam16|clk 897.1 MHz 762.5 MHz 1.115 1.311 -0.197 inferred Autoconstr_clkgroup_0
qam16|clk12p5MHz 802.7 MHz 476.6 MHz 1.246 2.098 -0.852 inferred Autoconstr_clkgroup_1
==========================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
---------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
---------------------------------------------------------------------------------------------------------------------------
qam16|clk qam16|clk | 1.115 -0.197 | No paths - | No paths - | No paths -
qam16|clk qam16|clk12p5MHz | Diff grp - | No paths - | No paths - | No paths -
qam16|clk12p5MHz qam16|clk12p5MHz | 1.246 -0.852 | No paths - | No paths - | No paths -
===========================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
No IO constraint found
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report for qam16
Mapping to part: xc4vsx35ff668-10
Cell usage:
FDR 44 uses
GND 1 use
MULT_AND 17 uses
MUXCY_L 17 uses
VCC 1 use
XORCY 17 uses
ddsqam 1 use
LUT1 1 use
LUT2 5 uses
LUT3 21 uses
LUT4 47 uses
I/O ports: 22
I/O primitives: 20
IBUF 2 uses
OBUF 18 uses
BUFGP 2 uses
I/O Register bits: 0
Register bits not including I/Os: 44 (0%)
Global Clock Buffers: 2 of 32 (6%)
Total load per clock:
qam16|clk: 10
qam16|clk12p5MHz: 35
Mapping Summary:
Total LUTs: 74 (0%)
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jun 24 09:48:19 2008
###########################################################]
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