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nco_vho_msim.tcl
if {[file exist [project env]] > 0} {project close}
if {[file exist "E:/zhangwei/fpga_pro/myown/9/nco.mpf"] == 0} {
project new E:/zhangwei/fpga_pro/myown/9/ nco
} else {
project open nco
}
# Create
entries
/README/1.1.1.2/Mon Jan 16 09:01:34 2006/-ko/
/fpga.c/1.1.1.2/Mon Jan 16 09:01:34 2006/-ko/
/fpga.h/1.1.1.1/Thu Sep 23 13:46:21 2004/-ko/
D
entries
/README/1.1.1.1/Sun Nov 03 00:29:54 2002/-ko/
/fpga.c/1.1.1.1/Sun Nov 03 00:29:55 2002/-ko/
/fpga.h/1.1.1.1/Mon Jun 10 16:09:10 2002/-ko/
D
entries
/README/1.1.1.2/Mon Jan 16 09:01:34 2006/-ko/
/fpga.c/1.1.1.2/Mon Jan 16 09:01:34 2006/-ko/
/fpga.h/1.1.1.1/Thu Sep 23 13:46:21 2004/-ko/
D
entries
/README/1.1.1.1/Sun Nov 03 00:29:54 2002/-ko/
/fpga.c/1.1.1.1/Sun Nov 03 00:29:55 2002/-ko/
/fpga.h/1.1.1.1/Mon Jun 10 16:09:10 2002/-ko/
D
makefile
#
# Makefile for Etrax-specific drivers
#
O_TARGET := drivers.o
export-objs := axisflashmap.o
obj-y :=
obj-$(CONFIG_ETRAX_VIRTEX_FPGA) += virtex.o
obj-$(CONFIG_ETRAX_ETHERNET) +
setup.scr
/* =================================================== */
/* Template .synopsys_dc.setup file for Xilinx designs */
/* For use with Synopsys FPGA Compiler. */
/* =======================
fx2_to_extsyncfifo.c
//modfiy at 2005-1-7
//with fpga
#pragma NOIV // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
// File:
.synopsys_dc.setup
/* =================================================== */
/* Template .synopsys_dc.setup file for Xilinx designs */
/* For use with Synopsys FPGA Compiler and Verilog */
/* =======================
.synopsys_dc.setup
/* =================================================== */
/* Template .synopsys_dc.setup file for Xilinx designs */
/* For use with Synopsys FPGA Compiler and VHDL */
/* =======================