.synopsys_dc.setup

xilinx官方PCIcore 有详细说明文档

/* =================================================== */
/* Template .synopsys_dc.setup file for Xilinx designs */
/*     For use with Synopsys FPGA Compiler and Verilog */
/* =================================================== */

/* ================================================= */
/* The Synopsys search path should be set to point   */
/* to the directories that contain the various       */  
/* synthesis libraries used by FPGA Compiler during  */
/* synthesis.                                        */
/* ================================================= */

XilinxInstall = get_unix_variable(XILINX);
SynopsysInstall = get_unix_variable(SYNOPSYS);

search_path = { .       \
        XilinxInstall + /synopsys/libraries/syn \
        SynopsysInstall + /libraries/syn }

                /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */
                /* Ensure that your UNIX environment */
                /* includes the two environment var- */
                /* iables: $XILINX (points to the    */
                /* Xilinx installation directory) and*/
                /* $SYNOPSYS (points to the Synopsys */
                /* installation directory.)          */  
                /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! */

/* ================================================= */
/* Define a work library in the current project dir  */
/* to hold temporary files and keep the project area */
/* uncluttered. Note: You must create a subdirectory */
/* in your project directory called WORK.            */  
/* ================================================= */
 
define_design_lib WORK -path ./WORK
hdlin_translate_off_skip_text = "true"

bus_extraction_style = "%s<%d:%d>"
bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"

cache_read = cache_write = "~"
cache_file_chmod_octal = "644"
cache_dir_chmod_octal = "755"

edifin_lib_logic_1_symbol = "VCC"
edifin_lib_logic_0_symbol = "GND"
edifout_ground_name = "GND"
edifout_ground_pin_name = "G"
edifout_power_name = "VCC"
edifout_power_pin_name = "P"
edifout_netlist_only = "true"
edifout_no_array = "true"
edifout_power_and_ground_representation = "cell"
edifout_write_properties_list = {"CLK1X_DUTY" "INIT_00" \
                                 "INIT_01" "INIT_02" \
                                 "INIT_03" "INIT_04" \
                                 "INIT_05" "INIT_06" \
                                 "INIT_07" "INIT_08" \
                                 "INIT_09" "INIT_0A" \
                                 "INIT_0B" "INIT_0C" \
                                 "INIT_0D" "INIT_0E" \
                                 "INIT_0F" "INIT" \
                                 "CLKDV_DIVIDE" \
                                 "IOB" "EQN" \
                                 "lut_function"}

/* ================================================= */
/* Set the link, target and synthetic library        */  
/* variables. Use synlibs (with the -dc switch) to   */
/* determine the link and target library settings.   */
/* You may like to copy this file to your project    */
/* directory, rename it ".synopsys_dc.setup" and     */  
/* append the output of synlibs. For example:        */  
/* synlibs xfpga_virtex-3 >> .synopsys_dc.setup      */
/* ================================================= */

symbol_library = {virtex.sdb}
link_library = {xfpga_virtex-6.db xdw_virtex.sldb}
target_library = {xfpga_virtex-6.db}
synthetic_library = {xdw_virtex.sldb standard.sldb}
 
define_design_lib xdw_virtex -path \
                  XilinxInstall + /synopsys/libraries/dw/lib/virtex