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FPGA 的代码
fpga-test.c
/*
fpga-test.c, need insmod s3c2410-fpga.o first.
author: wb
date: 2005-6-13 21:05
*/
#include
#include
#include
#include
fpga_transmitter.v
// RS-232 TX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
//`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations)
module uart_trans
fpga_uartrw.qsf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
fpga_receiver.v
// RS-232 RX module
// (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006
module uart_receiver(clk, RxD, RxD_data_ready, RxD_data);
input clk, RxD;
output RxD_data_ready; // onc clock pulse whe
fpga_uartrw.tcl
# Setup pin setting for EP2C5_EP2C8 main board
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
set_location_assi
fpga_uartrw.done
Wed May 07 10:10:09 2008
fpga_uartrw.bdf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
fpga_uartrw.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
pt