fpga_uartrw.bdf

FPGA的uart控制器的verilog源程序

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/
(header "graphic" (version "1.3"))
(pin
	(input)
	(rect -48 168 120 184)
	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
	(text "uart_rxd" (rect 5 0 45 12)(font "Arial" ))
	(pt 168 8)
	(drawing
		(line (pt 92 12)(pt 117 12)(line_width 1))
		(line (pt 92 4)(pt 117 4)(line_width 1))
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		(line (pt 117 4)(pt 121 8)(line_width 1))
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	(annotation_block (location)(rect -96 184 -48 200))
)
(pin
	(input)
	(rect -48 136 120 152)
	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
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	(pt 168 8)
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	(annotation_block (location)(rect -96 152 -48 168))
)
(pin
	(output)
	(rect 584 120 760 136)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "uart_txd" (rect 90 0 130 12)(font "Arial" ))
	(pt 0 8)
	(drawing
		(line (pt 0 8)(pt 52 8)(line_width 1))
		(line (pt 52 4)(pt 78 4)(line_width 1))
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	(annotation_block (location)(rect 760 136 808 152))
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	(rect 584 168 760 184)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "txd_busy_led" (rect 90 0 156 12)(font "Arial" ))
	(pt 0 8)
	(drawing
		(line (pt 0 8)(pt 52 8)(line_width 1))
		(line (pt 52 4)(pt 78 4)(line_width 1))
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		(line (pt 52 12)(pt 52 4)(line_width 1))
		(line (pt 78 4)(pt 82 8)(line_width 1))
		(line (pt 82 8)(pt 78 12)(line_width 1))
		(line (pt 78 12)(pt 82 8)(line_width 1))
	)
	(annotation_block (location)(rect 760 184 800 200))
)
(pin
	(output)
	(rect 376 240 552 256)
	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
	(text "rxd_ready_led" (rect 90 0 159 12)(font "Arial" ))
	(pt 0 8)
	(drawing
		(line (pt 0 8)(pt 52 8)(line_width 1))
		(line (pt 52 4)(pt 78 4)(line_width 1))
		(line (pt 52 12)(pt 78 12)(line_width 1))
		(line (pt 52 12)(pt 52 4)(line_width 1))
		(line (pt 78 4)(pt 82 8)(line_width 1))
		(line (pt 82 8)(pt 78 12)(line_width 1))
		(line (pt 78 12)(pt 82 8)(line_width 1))
	)
	(annotation_block (location)(rect 552 256 592 272))
)
(symbol
	(rect 376 96 552 192)
	(text "uart_transmitter" (rect 5 0 82 12)(font "Arial" ))
	(text "inst" (rect 8 80 25 92)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "clk" (rect 0 0 14 12)(font "Arial" ))
		(text "clk" (rect 21 27 35 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "TxD_start" (rect 0 0 48 12)(font "Arial" ))
		(text "TxD_start" (rect 21 43 69 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "TxD_data[7..0]" (rect 0 0 73 12)(font "Arial" ))
		(text "TxD_data[7..0]" (rect 21 59 94 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 3))
	)
	(port
		(pt 176 32)
		(output)
		(text "TxD" (rect 0 0 20 12)(font "Arial" ))
		(text "TxD" (rect 135 27 155 39)(font "Arial" ))
		(line (pt 176 32)(pt 160 32)(line_width 1))
	)
	(port
		(pt 176 48)
		(output)
		(text "TxD_busy" (rect 0 0 50 12)(font "Arial" ))
		(text "TxD_busy" (rect 105 43 155 55)(font "Arial" ))
		(line (pt 176 48)(pt 160 48)(line_width 1))
	)
	(parameter
		"ClkFrequency"
		"50000000"
		""
	)
	(parameter
		"Baud"
		"115200"
		""
	)
	(parameter
		"RegisterInputData"
		"1"
		""
	)
	(parameter
		"BaudGeneratorAccWidth"
		"16"
		""
	)
	(drawing
		(rectangle (rect 16 16 160 80)(line_width 1))
	)
	(annotation_block (parameter)(rect 376 -8 560 64))
)
(symbol
	(rect 160 112 320 208)
	(text "uart_receiver" (rect 5 0 69 12)(font "Arial" ))
	(text "inst1" (rect 8 80 31 92)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "clk" (rect 0 0 14 12)(font "Arial" ))
		(text "clk" (rect 21 27 35 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "RxD" (rect 0 0 22 12)(font "Arial" ))
		(text "RxD" (rect 21 43 43 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 160 32)
		(output)
		(text "RxD_data_ready" (rect 0 0 83 12)(font "Arial" ))
		(text "RxD_data_ready" (rect 56 27 139 39)(font "Arial" ))
		(line (pt 160 32)(pt 144 32)(line_width 1))
	)
	(port
		(pt 160 48)
		(output)
		(text "RxD_data[7..0]" (rect 0 0 75 12)(font "Arial" ))
		(text "RxD_data[7..0]" (rect 64 43 139 55)(font "Arial" ))
		(line (pt 160 48)(pt 144 48)(line_width 3))
	)
	(parameter
		"ClkFrequency"
		"50000000"
		""
	)
	(parameter
		"Baud"
		"115200"
		""
	)
	(parameter
		"Baud8"
		""
		""
	)
	(parameter
		"Baud8GeneratorAccWidth"
		"16"
		""
	)
	(drawing
		(rectangle (rect 16 16 144 80)(line_width 1))
	)
	(annotation_block (parameter)(rect 80 -16 264 56))
)
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(connector
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(connector
	(pt 320 160)
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	(bus)
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