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FPGA 的代码
uart_ctrl.pro
J:\712\AIS\programme\FPGA\FPGA_Part test\uart8\designer\impl1\uart_ctrl_fp
Singl
fifo_dp_1k.xco
# Xilinx CORE Generator 5.1i
# Username = a0214588
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = C:\userdata\Video_Imaging\Zeno\EVM\Video\OSD_FPGA\osd_fpga
# ExpandedProjectPath = C:\userdata\
ram_128x24.xco
# Xilinx CORE Generator 5.1.03i
# Username = a0214588
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = C:\userdata\Video_Imaging\Zeno\EVM\Video\OSD_FPGA\osd_fpga
# ExpandedProjectPath = C:\userda
adc_interface.v
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module adc_interface
(input clock, input reset, input enable,
input wire [6:0] seria
mrfm_proc.v
`include "mrfm.vh"
`include "../../../firmware/include/fpga_regs_common.v"
`include "../../../firmware/include/fpga_regs_standard.v"
module mrfm_proc (input clock, input reset, input enable,
inp
icpld.v
// Quartus Verilog Template
// Counter with synchronous load and active low asynchronous clear
module icpld (
input [2:0] SWITCH_MODE,RAM_ADDR_LATCH,
input [3:0] RAM_DATA_SEL,MCU_CODE,
in
pwmtest.hif
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
33
1676
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
pwm_fpga
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# ca
fsk_modelsim.xrf
vendor_name = ModelSim
source_file = 1, E:/My_Design/FPGA/FSK/FSK_Mod.vhd
source_file = 1, E:/My_Design/FPGA/FSK/Carrier.vhd
source_file = 1, E:/My_Design/FPGA/FSK/FSK.bdf
source_file = 1, E:/My_D