fifo_dp_1k.xco

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

# Xilinx CORE Generator 5.1i
# Username = a0214588
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = C:\userdata\Video_Imaging\Zeno\EVM\Video\OSD_FPGA\osd_fpga
# ExpandedProjectPath = C:\userdata\Video_Imaging\Zeno\EVM\Video\OSD_FPGA\osd_fpga
# OverwriteFiles = true
# Core name: fifo_dp_1k
# Number of Primitives in design: 238
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 76
# Number of LUTs used in design: 76
# Number of REG used in design: 92
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 2
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracket
SET SimulationOutputProducts = Verilog VHDL
SET XilinxFamily = Spartan2
SET OutputOption = DesignFlow
SET DesignFlow = Vhdl
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SELECT Asynchronous_FIFO Spartan2 Xilinx,_Inc. 4.0
CSET read_error_sense = active_high
CSET read_count_width = 2
CSET write_acknowledge = false
CSET create_rpm = false
CSET read_acknowledge = false
CSET read_count = false
CSET write_error = false
CSET almost_full_flag = false
CSET almost_empty_flag = false
CSET memory_type = block
CSET read_error = false
CSET fifo_depth = 255
CSET component_name = fifo_dp_1k
CSET input_data_width = 32
CSET write_count = true
CSET write_acknowledge_sense = active_high
CSET read_acknowledge_sense = active_high
CSET write_error_sense = active_high
CSET write_count_width = 8
GENERATE