ram_128x24.xco

TI evm642的源码,给那些没有买TI的评估板,却想要评估板程序的人.

# Xilinx CORE Generator 5.1.03i
# Username = a0214588
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = C:\userdata\Video_Imaging\Zeno\EVM\Video\OSD_FPGA\osd_fpga
# ExpandedProjectPath = C:\userdata\Video_Imaging\Zeno\EVM\Video\OSD_FPGA\osd_fpga
# OverwriteFiles = true
# Core name: ram_128x24
# Number of Primitives in design: 2
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 0
# Number of LUTs used in design: 0
# Number of REG used in design: 0
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 2
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracket
SET SimulationOutputProducts = Verilog VHDL
SET XilinxFamily = Spartan2
SET OutputOption = DesignFlow
SET DesignFlow = Vhdl
SET FlowVendor = Foundation_iSE
SET FormalVerification = None
SELECT Dual_Port_Block_Memory Spartan2 Xilinx,_Inc. 4.0
CSET primitive_selection = Optimize_For_Area
CSET port_a_active_clock_edge = Rising_Edge_Triggered
CSET port_a_additional_output_pipe_stages = 0
CSET port_b_active_clock_edge = Rising_Edge_Triggered
CSET port_a_enable_pin = false
CSET port_a_write_enable_polarity = Active_High
CSET port_a_initialization_pin_polarity = Active_High
CSET global_init_value = 0
CSET port_a_init_pin = false
CSET select_primitive = 4kx1
CSET port_b_enable_pin = false
CSET width_b = 24
CSET port_a_init_value = 0
CSET width_a = 24
CSET depth_b = 128
CSET port_a_register_inputs = false
CSET component_name = ram_128x24
CSET depth_a = 128
CSET configuration_port_b = Read_Only
CSET port_b_write_enable_polarity = Active_High
CSET configuration_port_a = Write_Only
CSET port_b_init_value = 0
CSET port_b_handshaking_pins = false
CSET port_b_register_inputs = false
CSET port_b_initialization_pin_polarity = Active_High
CSET load_init_file = false
CSET port_a_enable_pin_polarity = Active_High
CSET port_a_handshaking_pins = false
CSET port_b_additional_output_pipe_stages = 0
CSET port_b_enable_pin_polarity = Active_High
CSET port_b_init_pin = false
CSET write_mode_port_b = Read_After_Write
CSET write_mode_port_a = Read_After_Write
GENERATE