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FPGA 的代码
fpga_loadercfg_c.c
/* Do *not* directly modify this file. It was */
/* generated by the Configuration Tool; any */
/* changes risk being overwritten. */
/* INPUT fpga_loader.cdb */
/* Includ
fpga_core_tb.v
// fpga_core_tb.v
`timescale 1ns/100ps
module fpga_core_tb ( );
//input :
reg tb_RESET;
reg tb_reset;
reg tb_frame_valid;
reg tb_li
fpga_core_syn.prj
#add_file options
add_file -verilog "H:/fpga_test/fpga_fifo_0122_02/smartgen/fifo_fpga1280x8/fifo_fpga1280x8.v"
add_file -verilog "H:/fpga_test/fpga_fifo_0122_02/hdl/fifo_fpga_1280x8.v"
#device o
fpga_core_sdc.sdc
# Top Level Design Parameters
# Clocks
create_clock -period 10.000000 -waveform {0.000000 5.000000} clk_48
create_clock -period 10.000000 -waveform {0.000000 5.000000} clk_54
# False Paths B
fpga_dsp_portlink.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu