fpga_core_sdc.sdc

来自「可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除6」· SDC 代码 · 共 27 行

# Top Level Design Parameters

# Clocks

create_clock -period 10.000000 -waveform {0.000000 5.000000} clk_48
create_clock -period 10.000000 -waveform {0.000000 5.000000} clk_54

# False Paths Between Clocks


# False Path Constraints


# Maximum Delay Constraints


# Multicycle Constraints


# Virtual Clocks
# Output Load Constraints
# Driving Cell Constraints
# Wire Loads
# set_wire_load_mode top

# Other Constraints