代码搜索结果

|USB_FPGA gclk => fifordaddr[8].CLK gclk => fifordaddr[7].CLK gclk => fifordaddr[6].CLK gclk => fifordaddr[5].CLK gclk => fifordaddr[4].CLK gclk => fifordaddr[3].CLK gclk => fifordaddr[2].CLK

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o

Analysis & Synthesis Status : Successful - Tue Oct 30 20:34:36 2007 Quartus II Version : 5.1 Build 176 10/26/2005 SJ Web Edition Revision Name : USB_FPGA Top-level Entity Name : USB_FPGA Family :

Flow report for USB_FPGA Tue Oct 30 20:35:04 2007 Version 5.1 Build 176 10/26/2005 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Fl