usb_fpga.sim.qmsg

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 30 20:33:32 2007 " "Info: Processing started: Tue Oct 30 20:33:32 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off USB_FPGA -c USB_FPGA " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off USB_FPGA -c USB_FPGA" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Error" "ESIM_QSYN_QTAN_NOT_RUN_FOR_ATOM" "USB_FPGA " "Error: Run Analysis and Synthesis (quartus_map) through Technology Mapping followed by Timing Analyzer (quartus_tan) on top level entity \"USB_FPGA\" before running timing simulation in Simulator (quartus_sim)" {  } {  } 0 0 "Run Analysis and Synthesis (quartus_map) through Technology Mapping followed by Timing Analyzer (quartus_tan) on top level entity \"%1!s!\" before running timing simulation in Simulator (quartus_sim)" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Simulator 1  0 s Quartus II " "Error: Quartus II Simulator was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Oct 30 20:33:32 2007 " "Error: Processing ended: Tue Oct 30 20:33:32 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:00 " "Error: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}