usb_fpga.hier_info

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

|USB_FPGA
gclk => fifordaddr[8].CLK
gclk => fifordaddr[7].CLK
gclk => fifordaddr[6].CLK
gclk => fifordaddr[5].CLK
gclk => fifordaddr[4].CLK
gclk => fifordaddr[3].CLK
gclk => fifordaddr[2].CLK
gclk => fifordaddr[1].CLK
gclk => fifordaddr[0].CLK
gclk => led4buf.CLK
gclk => data2usb[15].CLK
gclk => data2usb[14].CLK
gclk => data2usb[13].CLK
gclk => data2usb[12].CLK
gclk => data2usb[11].CLK
gclk => data2usb[10].CLK
gclk => data2usb[9].CLK
gclk => data2usb[8].CLK
gclk => data2usb[7].CLK
gclk => data2usb[6].CLK
gclk => data2usb[5].CLK
gclk => data2usb[4].CLK
gclk => data2usb[3].CLK
gclk => data2usb[2].CLK
gclk => data2usb[1].CLK
gclk => data2usb[0].CLK
gclk => FX2FD[15]~reg0.CLK
gclk => FX2FD[14]~reg0.CLK
gclk => FX2FD[13]~reg0.CLK
gclk => FX2FD[12]~reg0.CLK
gclk => FX2FD[11]~reg0.CLK
gclk => FX2FD[10]~reg0.CLK
gclk => FX2FD[9]~reg0.CLK
gclk => FX2FD[8]~reg0.CLK
gclk => FX2FD[7]~reg0.CLK
gclk => FX2FD[6]~reg0.CLK
gclk => FX2FD[5]~reg0.CLK
gclk => FX2FD[4]~reg0.CLK
gclk => FX2FD[3]~reg0.CLK
gclk => FX2FD[2]~reg0.CLK
gclk => FX2FD[1]~reg0.CLK
gclk => FX2FD[0]~reg0.CLK
gclk => process1~0.CLK
gclk => process1~1.CLK
gclk => process1~3.CLK
gclk => process1~5.CLK
gclk => process1~7.CLK
gclk => process1~9.CLK
gclk => process1~11.CLK
gclk => process1~13.CLK
gclk => process1~15.CLK
gclk => process1~17.CLK
gclk => process1~19.CLK
gclk => process1~21.CLK
gclk => process1~23.CLK
gclk => process1~25.CLK
gclk => process1~27.CLK
gclk => process1~29.CLK
gclk => fifowraddr[7].CLK
gclk => fifowraddr[8].CLK
gclk => fifordaddr[9].CLK
gclk => fifowraddr[6].CLK
gclk => fifowraddr[5].CLK
gclk => fifowraddr[4].CLK
gclk => fifowraddr[3].CLK
gclk => fifowraddr[2].CLK
gclk => fifowraddr[1].CLK
gclk => fifowraddr[0].CLK
gclk => led2buf.CLK
gclk => fifowraddr[9].CLK
gclk => fifomemory.CLK0
gclk => fifomemory.CLK1
RESETFPGA => fifordaddr[8].ACLR
RESETFPGA => fifordaddr[7].ACLR
RESETFPGA => fifordaddr[6].ACLR
RESETFPGA => fifordaddr[5].ACLR
RESETFPGA => fifordaddr[4].ACLR
RESETFPGA => fifordaddr[3].ACLR
RESETFPGA => fifordaddr[2].ACLR
RESETFPGA => fifordaddr[1].ACLR
RESETFPGA => fifordaddr[0].ACLR
RESETFPGA => led4buf.PRESET
RESETFPGA => fifoff~2.OUTPUTSELECT
RESETFPGA => fifowraddr[9].ACLR
RESETFPGA => fifomemory~0.OUTPUTSELECT
RESETFPGA => fifoef~0.OUTPUTSELECT
RESETFPGA => led2buf.PRESET
RESETFPGA => fifowraddr[0].ACLR
RESETFPGA => fifowraddr[1].ACLR
RESETFPGA => fifowraddr[2].ACLR
RESETFPGA => fifowraddr[3].ACLR
RESETFPGA => fifowraddr[4].ACLR
RESETFPGA => fifowraddr[5].ACLR
RESETFPGA => fifowraddr[6].ACLR
RESETFPGA => fifowraddr[7].ACLR
RESETFPGA => fifowraddr[8].ACLR
RESETFPGA => fifordaddr[9].ACLR
RESETFPGA => FX2FD[15]~reg0.ENA
RESETFPGA => FX2FD[14]~reg0.ENA
RESETFPGA => FX2FD[13]~reg0.ENA
RESETFPGA => FX2FD[12]~reg0.ENA
RESETFPGA => FX2FD[11]~reg0.ENA
RESETFPGA => FX2FD[10]~reg0.ENA
RESETFPGA => FX2FD[9]~reg0.ENA
RESETFPGA => FX2FD[8]~reg0.ENA
RESETFPGA => FX2FD[7]~reg0.ENA
RESETFPGA => FX2FD[6]~reg0.ENA
RESETFPGA => FX2FD[5]~reg0.ENA
RESETFPGA => FX2FD[4]~reg0.ENA
RESETFPGA => FX2FD[3]~reg0.ENA
RESETFPGA => FX2FD[2]~reg0.ENA
RESETFPGA => FX2FD[1]~reg0.ENA
RESETFPGA => FX2FD[0]~reg0.ENA
RESETFPGA => process1~0.ENA
RESETFPGA => process1~1.ENA
RESETFPGA => process1~3.ENA
RESETFPGA => process1~5.ENA
RESETFPGA => process1~7.ENA
RESETFPGA => process1~9.ENA
RESETFPGA => process1~11.ENA
RESETFPGA => process1~13.ENA
RESETFPGA => process1~15.ENA
RESETFPGA => process1~17.ENA
RESETFPGA => process1~19.ENA
RESETFPGA => process1~21.ENA
RESETFPGA => process1~23.ENA
RESETFPGA => process1~25.ENA
RESETFPGA => process1~27.ENA
RESETFPGA => process1~29.ENA
RESETFPGA => fifomemory.CLR1
FX2FD[0] <= process1~31
FX2FD[1] <= process1~30
FX2FD[2] <= process1~28
FX2FD[3] <= process1~26
FX2FD[4] <= process1~24
FX2FD[5] <= process1~22
FX2FD[6] <= process1~20
FX2FD[7] <= process1~18
FX2FD[8] <= process1~16
FX2FD[9] <= process1~14
FX2FD[10] <= process1~12
FX2FD[11] <= process1~10
FX2FD[12] <= process1~8
FX2FD[13] <= process1~6
FX2FD[14] <= process1~4
FX2FD[15] <= process1~2
FX2ADR[0] => SRAMADR[0].DATAIN
FX2ADR[1] => SRAMADR[1].DATAIN
FX2ADR[2] => SRAMADR[2].DATAIN
FX2ADR[3] => SRAMADR[3].DATAIN
FX2ADR[4] => SRAMADR[4].DATAIN
FX2ADR[5] => SRAMADR[5].DATAIN
FX2ADR[6] => SRAMADR[6].DATAIN
FX2ADR[7] => SRAMADR[7].DATAIN
FX2ADR[8] => SRAMADR[8].DATAIN
CTL0_FLAGA => fifomemory~0.DATAA
CTL0_FLAGA => fifowraddr[8].ENA
CTL0_FLAGA => fifowraddr[7].ENA
CTL0_FLAGA => fifowraddr[6].ENA
CTL0_FLAGA => fifowraddr[5].ENA
CTL0_FLAGA => fifowraddr[4].ENA
CTL0_FLAGA => fifowraddr[3].ENA
CTL0_FLAGA => fifowraddr[2].ENA
CTL0_FLAGA => fifowraddr[1].ENA
CTL0_FLAGA => fifowraddr[0].ENA
CTL0_FLAGA => fifowraddr[9].ENA
CTL0_FLAGA => led2buf.ENA
CTL1_FLAGB => fifordaddr[9].ENA
CTL1_FLAGB => fifordaddr[8].ENA
CTL1_FLAGB => fifordaddr[7].ENA
CTL1_FLAGB => fifordaddr[6].ENA
CTL1_FLAGB => fifordaddr[5].ENA
CTL1_FLAGB => fifordaddr[4].ENA
CTL1_FLAGB => fifordaddr[3].ENA
CTL1_FLAGB => fifordaddr[2].ENA
CTL1_FLAGB => fifordaddr[1].ENA
CTL1_FLAGB => fifordaddr[0].ENA
CTL1_FLAGB => led4buf.ENA
CTL1_FLAGB => fifomemory.ENA1
CTL2_FLAGC => process1~0.DATAIN
CTL2_FLAGC => process1~1.DATAIN
CTL2_FLAGC => process1~3.DATAIN
CTL2_FLAGC => process1~5.DATAIN
CTL2_FLAGC => process1~7.DATAIN
CTL2_FLAGC => process1~9.DATAIN
CTL2_FLAGC => process1~11.DATAIN
CTL2_FLAGC => process1~13.DATAIN
CTL2_FLAGC => process1~15.DATAIN
CTL2_FLAGC => process1~17.DATAIN
CTL2_FLAGC => process1~19.DATAIN
CTL2_FLAGC => process1~21.DATAIN
CTL2_FLAGC => process1~23.DATAIN
CTL2_FLAGC => process1~25.DATAIN
CTL2_FLAGC => process1~27.DATAIN
CTL2_FLAGC => process1~29.DATAIN
CTL3 => ~NO_FANOUT~
CTL4 => ~NO_FANOUT~
CTL5 => ~NO_FANOUT~
RDY0_SLRD <= fifoef~0.DB_MAX_OUTPUT_PORT_TYPE
RDY1_SLWR <= fifoff~2.DB_MAX_OUTPUT_PORT_TYPE
RDY2 <= <GND>
RDY3 <= <GND>
RDY4 <= <GND>
RDY5 <= <GND>
SRAMFD[0] <= <GND>
SRAMFD[1] <= <GND>
SRAMFD[2] <= <GND>
SRAMFD[3] <= <GND>
SRAMFD[4] <= <GND>
SRAMFD[5] <= <GND>
SRAMFD[6] <= <GND>
SRAMFD[7] <= <GND>
SRAMFD[8] <= <GND>
SRAMFD[9] <= <GND>
SRAMFD[10] <= <GND>
SRAMFD[11] <= <GND>
SRAMFD[12] <= <GND>
SRAMFD[13] <= <GND>
SRAMFD[14] <= <GND>
SRAMFD[15] <= <GND>
SRAMADR[0] <= FX2ADR[0].DB_MAX_OUTPUT_PORT_TYPE
SRAMADR[1] <= FX2ADR[1].DB_MAX_OUTPUT_PORT_TYPE
SRAMADR[2] <= FX2ADR[2].DB_MAX_OUTPUT_PORT_TYPE
SRAMADR[3] <= FX2ADR[3].DB_MAX_OUTPUT_PORT_TYPE
SRAMADR[4] <= FX2ADR[4].DB_MAX_OUTPUT_PORT_TYPE
SRAMADR[5] <= FX2ADR[5].DB_MAX_OUTPUT_PORT_TYPE
SRAMADR[6] <= FX2ADR[6].DB_MAX_OUTPUT_PORT_TYPE
SRAMADR[7] <= FX2ADR[7].DB_MAX_OUTPUT_PORT_TYPE
SRAMADR[8] <= FX2ADR[8].DB_MAX_OUTPUT_PORT_TYPE
SRAMADR[9] <= <GND>
SRAMADR[10] <= <GND>
SRAMADR[11] <= <GND>
SRAMADR[12] <= <GND>
SRAMADR[13] <= <GND>
SRAMADR[14] <= <GND>
SRAMADR[15] <= <GND>
SRAMADR[16] <= <GND>
SRAMADR[17] <= <GND>
SRAMWE <= <GND>
SRAMCE <= <GND>
SRAMOE <= <GND>
SRAMUB <= <GND>
SRAMLB <= <GND>
LED1 <= KEY1.DB_MAX_OUTPUT_PORT_TYPE
LED2 <= led2buf.DB_MAX_OUTPUT_PORT_TYPE
LED3 <= KEY3.DB_MAX_OUTPUT_PORT_TYPE
LED4 <= led4buf.DB_MAX_OUTPUT_PORT_TYPE
KEY1 => LED1.DATAIN
KEY2 => ~NO_FANOUT~
KEY3 => LED3.DATAIN
KEY4 => ~NO_FANOUT~