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Classic Timing Analyzer report for fpga_uartrw Wed May 07 10:10:09 2008 Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version --------------------- ; Table of Contents ; ---------------

# Setup pin setting for EP2C5_EP2C8 main board set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF set_location_assi

Fitter Status : Successful - Wed May 07 10:09:57 2008 Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version Revision Name : fpga_uartrw Top-level Entity Name : fpga_uartrw Family : Cyclone

Analysis & Synthesis report for fpga_uartrw Wed May 07 10:09:52 2008 Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version --------------------- ; Table of Contents ; ------------------

// RS-232 TX module // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 //`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations) module uart_trans

Analysis & Synthesis Status : Successful - Wed May 07 10:09:52 2008 Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version Revision Name : fpga_uartrw Top-level Entity Name : fpga_uartrw Fa

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// RS-232 RX module // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005, 2006 module uart_receiver(clk, RxD, RxD_data_ready, RxD_data); input clk, RxD; output RxD_data_ready; // onc clock pulse whe

Extra Info: Performing register packing on registers with non-logic cell location assignments Extra Info: Completed register packing on registers with non-logic cell location assignments Extra Info:

Fitter report for fpga_uartrw Wed May 07 10:09:57 2008 Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Lega