fpga_uartrw.map.summary

来自「FPGA的uart控制器的verilog源程序」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Wed May 07 10:09:52 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : fpga_uartrw
Top-level Entity Name : fpga_uartrw
Family : Cyclone II
Total logic elements : 75
    Total combinational functions : 75
    Dedicated logic registers : 66
Total registers : 66
Total pins : 5
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0