fpga_uartrw.tan.summary

FPGA的uart控制器的verilog源程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.284 ns
From           : uart_rxd
To             : uart_receiver:inst1|RxD_sync_inv[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.465 ns
From           : uart_transmitter:inst|state[1]
To             : txd_busy_led
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.018 ns
From           : uart_rxd
To             : uart_receiver:inst1|RxD_sync_inv[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 234.91 MHz ( period = 4.257 ns )
From           : uart_receiver:inst1|bit_spacing[0]
To             : uart_receiver:inst1|RxD_data[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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