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FPGA 的代码
prev_cmp_fpga_pro.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quart
prev_cmp_fpga_pro.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quart
cpld.vhd
--fpga FPP(fast passive parallel) configuration
--fpga_conf_done in ：The FPGA will release the pin high when configuration is successful.配置成功后置高
--fpga_nstatus in ：FPGA pulls the pin low if a con
stfpga.c
/*****************************************************************************
File name : stfpga.c
Description : Programmation of fpga on MB282 evaluation board
COPYRIGHT (C) ST-Microelectroni
stfpga.c
/*****************************************************************************
File name : stfpga.c
Description : Programmation of fpga on MB282 evaluation board
COPYRIGHT (C) ST-Microelectroni
netlist.lst
e:\program\fpga_program\for_fpga\can\ise\canbus\can_top.ngc 1105409657
OK
coregen.log
# Xilinx CORE Generator 6.1i
# User = 刘韬
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\program\FPGA_PROGRAM\FOR_FPGA\vga_lcd\vga\coregen.log
# bu
fx2_to_extsyncfifo.plg
礦ision2 Build Log
Project:
D:\FPGA\FPGA&USB\fifo_FPGA\FX2_to_extsyncFIFO.uv2
Project File Date: 03/12/2008
Output:
demo.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
coregen.log
# Xilinx CORE Generator 6.1i
# User = 刘韬
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\program\FPGA_PROGRAM\FOR_FPGA\vga_lcd\vga\coregen.log
# bu