cpld.vhd

用CPLD做了个FPGA的FPP下载时序

--fpga FPP(fast passive parallel) configuration
--fpga_conf_done	in  ：The FPGA will release the pin high when configuration is successful.配置成功后置高
--fpga_nstatus		in  ：FPGA pulls the pin low if a configuration error occurs.配置出错此脚被拉低
--fpga_dclk			out ：Clock input data to the FPGA device during configuration.时钟信号
--fpga_nconfig		out ：A low pulse resets the FPGA and initiates configuration. 一个低脉冲启动配置
--fpga_data(7..0)	out ：Data output from the flash to the FPGA device during configuration.数据信号 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-------------------------------------------------------------------------------------
ENTITY cpld_test IS
PORT (	
		mclk			:	in		std_logic;
		cpu_writ		:	in		std_logic;
		cpu_cs			:	in		std_logic;
		cpu_oe			:	in		std_logic;
		cpld_rst		:	in		std_logic;
		fpga_data		:	inout	std_logic_vector(7 downto 0);
		arm_data		:	inout	std_logic_vector(7 downto 0);
		cpu_addr		:	in		std_logic_vector(15 downto 0);
		fpga_conf_done 	: 	in	 	std_logic;
		fpga_nstatus	:	inout 	std_logic;
		fpga_nconfig	:	inout 	std_logic;
		fpga_dclk		:	out 	std_logic;
		lcd_sign		:	out		std_logic		
);
END cpld_test;
---------------------------------------------------------------------------------------
ARCHITECTURE config OF cpld_test IS
		signal temp1 	: 	unsigned(7 downto 0);
		signal temp2 	: 	unsigned(7 downto 0);
		signal temp3 	: 	unsigned(7 downto 0);
		signal temp4 	: 	unsigned(7 downto 0);		
		signal temp5 	: 	unsigned(11 downto 0);		
		signal data1 	: 	unsigned(7 downto 0);
		signal data2 	: 	unsigned(7 downto 0);
		signal data3	: 	unsigned(7 downto 0);
		signal data4	: 	unsigned(7 downto 0);
		signal data5	: 	unsigned(11 downto 0);
		signal cpu_data	:	std_logic_vector(7 downto 0);
		signal cpld_sign:	std_logic;
		signal arm_sign	:	std_logic;
		signal clk_temp	:	std_logic;
		signal a		:	std_logic;
--时钟为24MHZ--24个时钟周期为1US
BEGIN
		data1<="00110011";--nconfig分频2U48个周期--启动时保持2Us的低电平
		data2<="11111111";--nstatus分频10U255个周期
		data3<="00010010";--nconfig到nstatus的延时0.75n18个周期
		data4<="01100000";--nstatus到dclk的延时4U96个周期
		data5<="100101100000";--100US后读fpga_conf_done的值		
		arm_data(0)<= cpld_sign when cpu_addr="0001000000000000" and cpu_oe = '0' and cpu_cs = '0'
				else--地址：0x1000启动标志
						'Z';--为高阻，以前设为0则总线上的数据低位始终为0，（错误）
		arm_data(1)<= fpga_conf_done when cpu_addr="0001000000000000" and cpu_oe = '0' and cpu_cs = '0'
				else--地址：0x1000终止标志
						'Z';
		arm_data<= fpga_data when cpu_addr="0001000000001011" and cpu_oe = '0' and cpu_cs = '0'
				else--地址：0x100b数据回传
						"ZZZZZZZZ";	
-------------------------------------------------------------------------------------																
		process(cpld_rst,mclk)
		begin
			if 	cpld_rst='1' then
				fpga_nstatus<='1';
				fpga_nconfig<='1';
				temp1<="00000000";
				temp2<="00000000";				
				temp3<="00000000";
				temp5<="000000000000";
				a<='0';
			elsif mclk'event and mclk='1' then				
---------------启动100US时读conf_done状态--------------------------------------	
				if temp5>= data5 then--100u--
					if  fpga_conf_done='1' then--配置成功后该脚为高
					fpga_nconfig<='Z';
					fpga_nstatus<='Z';
					end if;
					if fpga_nstatus='0' then--出错时该脚被拉低
					fpga_nconfig<='Z';
					end if;	
				else
					temp5<=temp5+1;
				end if;

				if a='0' then
					fpga_nconfig<='0';--一个低脉冲启动配置
---------------nconfig到nstatus的延时0.75n18个周期置为低电平-------------------				
					if temp3>= data3 and fpga_nconfig='0' and fpga_conf_done='0' then
						fpga_nstatus<='0';
					else
 						temp3<=temp3+1;
					end if;
---------------nconfig保持2US的的低电平后置高----------------------------------------								
					if temp1 >= data1 and fpga_conf_done='0' then
						fpga_nconfig<='1';
					else
						temp1<=temp1+1;
					end if;
---------------nstatus保持10US的的低电平后置高----------------------------------------				
					if temp2 >= data2 and fpga_conf_done='0' then
						fpga_nstatus<='1';
						a<='1';
					else
						temp2<=temp2+1;
					end if;
				end if;
			end if;
		end process;
-------------------------------------------------------------------------------------
		process(cpld_rst,cpu_writ)--数据传输
		begin
			if 	cpld_rst='1' then
				cpu_data<="ZZZZZZZZ"; 
			elsif cpu_writ'event and cpu_writ='1' then
				if cpu_addr="0001000000001001" and cpu_cs='0' then--地址为1009
					cpu_data<=arm_data;
				end if;
			end if;
		end process;
-------------------------------------------------------------------------------------
		process(cpld_rst,cpu_writ)--数据传输标志
		begin
			if 	cpld_rst='1' then
				arm_sign<='0'; 
			elsif cpu_writ'event and cpu_writ='1' then
				if cpu_addr="0001000000001010" and cpu_cs='0' then--地址为100a
					arm_sign<=arm_data(0);
				end if;
			end if;
		end process;
-------------------------------------------------------------------------------------
		process(clk_temp,cpld_rst)--数据传到FPGA
		begin
			if cpld_rst='1' then
				fpga_data<="ZZZZZZZZ";
				cpld_sign<='0';
				lcd_sign<='0';
			elsif clk_temp'event and clk_temp='1' then
				if fpga_nconfig='1' and fpga_conf_done='0' and fpga_nstatus ='1'
					and arm_sign='1' then
						fpga_data<=cpu_data;
						lcd_sign<='1';--传一个数灭
						cpld_sign<='1';
				else
						fpga_data<="ZZZZZZZZ";
						cpld_sign<='0';
						lcd_sign<='0';--不传亮
				end if;
			end if;
		end process;
--------------------------------------------------------------------------------------
		process(mclk,cpld_rst)--产生DCLK
		begin
			if cpld_rst='1' then
				clk_temp<='0';
				temp4<="00000000";				
			elsif mclk'event and mclk='1' then
				if fpga_nconfig='1' and fpga_conf_done='0' and fpga_nstatus ='1' 
					and arm_sign='1' then
						if temp4>=data4 then
							clk_temp<='1';
						else
							temp4<=temp4+1;
						end if;
				else
					clk_temp<='0';
				end if;
			end if;
		end process;
fpga_dclk<=clk_temp;
END config;