demo.map.qmsg

用硬件VHDL语言实现的串口通信的试验代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 25 17:22:39 2007 " "Info: Processing started: Mon Jun 25 17:22:39 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off demo -c demo " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off demo -c demo" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "demo.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file demo.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 demo " "Info: Found entity 1: demo" {  } { { "demo.bdf" "" { Schematic "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/demo.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen1250.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fen1250.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen1250-behave " "Info: Found design unit 1: fen1250-behave" {  } { { "fen1250.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/fen1250.vhd" 25 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fen1250 " "Info: Found entity 1: fen1250" {  } { { "fen1250.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/fen1250.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sentword.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sentword.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sentword-behave " "Info: Found design unit 1: sentword-behave" {  } { { "sentword.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/sentword.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sentword " "Info: Found entity 1: sentword" {  } { { "sentword.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/sentword.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "serialout.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file serialout.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 serialout-behave " "Info: Found design unit 1: serialout-behave" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 serialout " "Info: Found entity 1: serialout" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "serialout " "Info: Elaborating entity \"serialout\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|serialout\|state 5 " "Info: State machine \"\|serialout\|state\" contains 5 states" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|serialout\|state " "Info: Selected Auto state machine encoding method for state machine \"\|serialout\|state\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|serialout\|state " "Info: Encoding result for state machine \"\|serialout\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.x_stop " "Info: Encoded state bit \"state.x_stop\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.x_shift " "Info: Encoded state bit \"state.x_shift\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.x_wait " "Info: Encoded state bit \"state.x_wait\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.x_start " "Info: Encoded state bit \"state.x_start\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.x_idle " "Info: Encoded state bit \"state.x_idle\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serialout\|state.x_idle 00000 " "Info: State \"\|serialout\|state.x_idle\" uses code string \"00000\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serialout\|state.x_start 00011 " "Info: State \"\|serialout\|state.x_start\" uses code string \"00011\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serialout\|state.x_wait 00101 " "Info: State \"\|serialout\|state.x_wait\" uses code string \"00101\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serialout\|state.x_shift 01001 " "Info: State \"\|serialout\|state.x_shift\" uses code string \"01001\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|serialout\|state.x_stop 10001 " "Info: State \"\|serialout\|state.x_stop\" uses code string \"10001\"" {  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "serialout.vhd" "" { Text "E:/download/资料备份/史磊的资料/ic设计/fpga/FPGA开发板DEMO程序/003实验三 串口发送实验/serialout.vhd" 33 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "89 " "Info: Implemented 89 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "77 " "Info: Implemented 77 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 25 17:22:43 2007 " "Info: Processing ended: Mon Jun 25 17:22:43 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}