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FPGA 的代码
fpga_core.plg
@P: Worst Slack : -10.338
@P: fpga_core|clk_48 - Estimated Frequency : 52.4 MHz
@P: fpga_core|clk_48 - Requested Frequency : 100.0 MHz
@P: fpga_core|clk_48 - Estimated Period : 19.079
@P: fpg
fpga_core.msg
@TM:1200555804
@W: :"":0:0:0:-1|Although I/O insertion is disabled, Inferring tristate/bidirectional IO buffer to compensate device without internal tristate cell.
@TM:1210148494
@N: BN225 :"":0:
fpga_core.srr
#Build: Synplify 8.8A1, Build 015R, Apr 16 2007
#install: C:\Libero\Synplify\Synplify_88A1
#OS: Windows XP 5.1
#Hostname: ZHOUHUAGOU
#Implementation: synthesis
#Wed May 07 16:22:43 2008
$
fpga_core.srs
@E
@
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.7.5, Build 159R from Synplicity, Inc.
# Copyright 1994-2007 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written
fpga_core.sdf
(DELAYFILE
(SDFVERSION "OVI 2.1")
(DESIGN "fpga_core")
(DATE "123")
(VENDOR "ProASIC3")
(PROGRAM "Synplify")
(VERSION "8.8.0, Build 015R")
(DIVIDER /)
(VOLTAGE 2.500000:2.500000:2.500000)
(PR