fpga_core.msg

可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除68013a部分的程序

@TM:1200555804
@W:  :"":0:0:0:-1|Although I/O insertion is disabled, Inferring tristate/bidirectional IO buffer to compensate device without internal tristate cell. 
@TM:1210148494
@N: BN225 :"":0:0:0:-1|Writing default property annotation file H:\fpga_test\fpga_fifo_0122_02\synthesis\fpga_core.map.
@TM:1200555804
@N: MF249 :"":0:0:0:-1|Running in 32-bit mode.
@N: MT195 :"":0:0:0:-1|This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT197 :"":0:0:0:-1|Clock constraints cover only FF-to-FF paths associated with the clock..
@TM:1210148494
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":2:7:2:10|Synthesizing module AND2
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":8:7:8:11|Synthesizing module AND2A
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":20:7:20:10|Synthesizing module AND3
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":86:7:86:9|Synthesizing module AO1
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":104:7:104:10|Synthesizing module AO1C
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":122:7:122:10|Synthesizing module AOI1
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":854:7:854:10|Synthesizing module DFN1
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":860:7:860:12|Synthesizing module DFN1C0
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":908:7:908:14|Synthesizing module DFN1E1C0
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":932:7:932:12|Synthesizing module DFN1P0
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1094:7:1094:9|Synthesizing module GND
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1196:7:1196:9|Synthesizing module INV
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1202:7:1202:10|Synthesizing module MAJ3
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1238:7:1238:9|Synthesizing module MX2
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1262:7:1262:11|Synthesizing module NAND2
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1287:7:1287:12|Synthesizing module NAND3A
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1311:7:1311:11|Synthesizing module NOR2A
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1323:7:1323:10|Synthesizing module NOR3
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1329:7:1329:11|Synthesizing module NOR3A
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1353:7:1353:10|Synthesizing module OA1A
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1365:7:1365:10|Synthesizing module OA1C
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1377:7:1377:9|Synthesizing module OR2
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1383:7:1383:10|Synthesizing module OR2A
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1395:7:1395:9|Synthesizing module OR3
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1705:7:1705:9|Synthesizing module VCC
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1746:7:1746:11|Synthesizing module XNOR2
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1752:7:1752:11|Synthesizing module XNOR3
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1770:7:1770:10|Synthesizing module XOR2
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1776:7:1776:10|Synthesizing module XOR3
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1794:7:1794:10|Synthesizing module BUFF
@N: CG364 :"C:\Libero\Synplify\Synplify_88A1\lib\proasic\proasic3.v":1927:8:1927:16|Synthesizing module RAM512X18
@N: CG364 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":13:7:13:15|Synthesizing module fpga_core
@W: CL159 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":35:20:35:27|M
@W: CL169 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":104:2:104:7|M
@N:  :"h:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":154:2:154:7|M
@W: CL169 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":154:2:154:7|M
@W: CL171 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":225:2:225:7|M
@W: CL190 :"H:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":225:2:225:7|M
@N: MF238 :"h:\fpga_test\fpga_fifo_0122_02\hdl\fifo_fpga_1280x8.v":239:17:239:28|M
@N: CG364 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":5:7:5:21|Synthesizing module fifo_fpga1280x8
@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":247:9:247:15|M
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@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":441:9:441:15|M
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@W: CL168 :"H:\fpga_test\fpga_fifo_0122_02\smartgen\fifo_fpga1280x8\fifo_fpga1280x8.v":832:9:832:14|M
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