fpga_core.hpj

来自「可以在里面修改协议.主要是cmos---fpga--usb(68013a)中除6」· HPJ 代码 · 共 19 行

<!DOCTYPE SimulationProject SYSTEM "hdl-prj.dtd">
<SimulationProject ProductVersion="8.6c" Logfile="fpga_core.log" AutoParseProject="1" NameOfComponentToParse="fpga_core" Keyfile="verilog.key" Language="Verilog" DelayType="typical" AddTopLevelSignals="0" FileNamesShown="1" HideEmptyLists="1" ShowWatch="1" DumpWatch="0" InteractiveMode="1" ParametersAreWatchable="0" ClearLogBeforeCompile="1" CreateLogFileDuringSim="1" > 
  <FileList>
    <File>H:\fpga_test\test\new\hdl\fpga_core.v</File>
  </FileList>
  <DirList>
    <Directory>C:\Libero\WFL\</Directory>
    <Directory>H:\fpga_test\test\new\hdl</Directory>
  </DirList>
  <LibDirList>
    <Directory>C:\Libero\WFL\lib\verilog\</Directory>
    <Directory>C:\Libero\Designer/lib/vlog/proasic3.v</Directory>
  </LibDirList>
  <LibExtensionList>
    <Extension>.v</Extension>
    <Extension>.vo</Extension>
  </LibExtensionList>
</SimulationProject>