代码搜索:FPGA驱动

找到约 10,000 项符合「FPGA驱动」的源代码

代码结果 10,000
www.eeworm.com/read/148963/5707347

c tkdev_init.c

/* *---------------------------------------------------------------------- * T-Kernel * * Copyright (C) 2004 by Ken Sakamura. All rights reserved. * T-Kernel is distributed under the T-L
www.eeworm.com/read/488202/6498114

txt gw48使用readme.txt

“MUSIC”目录"梁祝"乐曲演奏示例使用说明 1、打开GW48-CK系统的电源; 2、下载MUSIC中的SONGER.SOF,到FPGA EPF10K20中; 3、用模式键选模式“1”,再按一次右侧的复位键; 4、使CLOCK9进入12MHz频率,以便控制音乐的音调; 5、使CLOCK2进入4Hz频率,以便控
www.eeworm.com/read/345513/11810660

tlg match_rec.tlg

Selecting top level module match_rec @N: CG364 :"E:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec\match_rec.v":21:7:21:15|Synthesizing
www.eeworm.com/read/345513/11810705

srr match_rec.srr

#Build: Synplify Pro 8.8.0.4, Build 008R, Dec 7 2006 #install: D:\Program\FPGA_software\Synplicity\fpga_8804 #OS: Windows XP 5.1 #Hostname: USER-73B7470377 #Implementation: match_rec #Fri Ju
www.eeworm.com/read/161054/5563529

c tkdev_init.c

/* *---------------------------------------------------------------------- * T-Kernel * * Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved. * T-Kernel is distributed under th
www.eeworm.com/read/471417/6892463

ucf system.ucf

############################################################################ ## This system.ucf file is generated by Base System Builder based on the ## settings in the selected Xilinx Board Definit
www.eeworm.com/read/215428/15061287

-

三星 K9F1G08 NAND FLASH 底层驱动, 没有上层的坏块处理和写平衡,处理器是LPC2294, 连接关系见图, 操作系统是ucos-ii,
www.eeworm.com/read/7658/126607

v system.v

module system ( fpga_0_RS232_Uart_1_RX_pin, fpga_0_RS232_Uart_1_TX_pin, fpga_0_LEDs_4Bit_GPIO_IO_pin, fpga_0_DIPSWs_4Bit_GPIO_IO_pin, fpga_0_PushButtons_5Bit_GPIO_IO_pin, fpga_0_PS2_Port
www.eeworm.com/read/17583/740410

v system.v

module system ( fpga_0_RS232_Uart_1_RX_pin, fpga_0_RS232_Uart_1_TX_pin, fpga_0_LEDs_4Bit_GPIO_IO_pin, fpga_0_DIPSWs_4Bit_GPIO_IO_pin, fpga_0_PushButtons_5Bit_GPIO_IO_pin, fpga_0_PS2_Port
www.eeworm.com/read/18466/790118

ref hdpdeps.ref

V1 7 FL F:/lqj/1/BulkIn/FPGA/Top.vhdl 2006/11/15.10:40:38 FL F:/lqj/1/FPGA/FPGA/Top.vhdl 2006/10/22.17:59:24 FL E:/study/software/FPGA/FPGA+USB/BulkIn/FPGA/Top.vhdl 2007/07/17.21:24:02 EN work/TOP