system.ucf

来自「source file application」· UCF 代码 · 共 44 行

############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=AJ15;
Net sys_clk_pin IOSTANDARD = LVCMOS25;
Net sys_rst_pin LOC=AH5;
Net sys_rst_pin IOSTANDARD = LVTTL;
## System level constraints
Net sys_clk_pin PERIOD = 10000 ps;
Net sys_rst_pin TIG;

## FPGA pin constraints
Net fpga_0_RS232_Uart_1_ctsN_pin LOC=AE8;
Net fpga_0_RS232_Uart_1_ctsN_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_ctsN_pin SLEW = SLOW;
Net fpga_0_RS232_Uart_1_ctsN_pin DRIVE = 8;
Net fpga_0_RS232_Uart_1_rtsN_pin LOC=AK8;
Net fpga_0_RS232_Uart_1_rtsN_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_sin_pin LOC=AJ8;
Net fpga_0_RS232_Uart_1_sin_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_sout_pin LOC=AE7;
Net fpga_0_RS232_Uart_1_sout_pin IOSTANDARD = LVCMOS25;
Net fpga_0_RS232_Uart_1_sout_pin SLEW = SLOW;
Net fpga_0_RS232_Uart_1_sout_pin DRIVE = 12;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin LOC=AG2;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin IOSTANDARD = LVTTL;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin SLEW = SLOW;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_clk_pin DRIVE = 8;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin LOC=AG1;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin IOSTANDARD = LVTTL;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin SLEW = SLOW;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_mouse_data_pin DRIVE = 8;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin LOC=AD6;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin IOSTANDARD = LVTTL;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin SLEW = SLOW;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_clk_pin DRIVE = 8;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin LOC=AD5;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin IOSTANDARD = LVTTL;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin SLEW = SLOW;
Net fpga_0_PS2_Ports_IO_ADAPTER_ps2_keyb_data_pin DRIVE = 8;