代码搜索：FPGA驱动
找到约 10,000 项符合「FPGA驱动」的源代码
代码结果 10,000
www.eeworm.com/read/303286/13818935
qmsg i2c.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
www.eeworm.com/read/302787/13827440
v ctrl_reg.v
// register desciption:
//reg[0]:clk_div_1; //FPGA 25mHZ 2分频；
//reg[1]:clk_div2; //CLK_MOD 4MHZ，六分频；
//reg[2]:REF_MEM_CTR, //reference memmory control reg;
//|15---|14---|13---|12---|11---|10---|
www.eeworm.com/read/149015/5704250
ucf system.ucf
############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definit
www.eeworm.com/read/343792/11927919
rpt pwmtest.tan.rpt
Timing Analyzer report for pwmtest
Thu May 31 18:54:45 2007
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
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; Table of Contents ;
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www.eeworm.com/read/210235/15203051
lfp led_water.lfp
# begin LFP file F:\FPGA\sp306\waterlight\LED_WATER.lfp
designfile led_water.v
parttype xc3s400-5-pq208
bus_delimiter -1;
set_busdelim_onsave 0;
www.eeworm.com/read/172417/5386918
ucf system.ucf
############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definit
www.eeworm.com/read/167507/5459669
ucf system.ucf
############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definit
www.eeworm.com/read/159314/5584979
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_startup is
port(
bus_reset : out vl_logic;
ghigh_b : out vl_logic;
gsr : out vl_lo
www.eeworm.com/read/159314/5585971
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity fpga_startup is
port(
bus_reset : out vl_logic;
ghigh_b : out vl_logic;
gsr : out vl_lo
www.eeworm.com/read/155551/5621043
ucf system.ucf
############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definit